High speed M-sequence generator and decoder circuit

• US 5,974,433 A
• Filed: 06/29/1984
• Issued: 10/26/1999
• Est. Priority Date: 06/29/1984
• Status: Expired due to Term

• Current Assignee: Lockheed Martin Corporation (Martin Marietta Corporation)
• Original Assignee: Lockheed Martin Corporation (Martin Marietta Corporation)
• Inventors: Currie, Robert John
• Primary Examiner(s): CANGIALOSI, SALVATORE A
• Application Number:
  US06/626,127
• Time in Patent Office: 5,597 Days
• Field of Search: 364/717, 178/22.19, 375/1, 375/115, 370/18, 358/717.01, 708/250-256
• US Class Current: 708/252
• CPC Class Codes: G06F 2207/581 Generating an LFSR sequence, e.g. an m-sequence; sequence may be generated without LFSR, e.g. using Galois Field arithmetic
• CPC Class Codes: G06F 7/584 using finite field arithmetic, e.g. using a linear feedback shift register

Abstract

This circuit permits M-sequence signals to be generated and decoded very fast while using relatively low power, low speed circuitry components.

Claims

1. A M-sequence code generator comprising,

a plurality of linear feedback shift registers for generating pseudo-random signals,

multiplexer means coupled to said registers for receiving said signals and for transmitting said signals therethrough in a multiplexed manner,

gate means coupled to the output of said multiplexer means, for receiving said signals from said multiplexer means, and

clock means coupled to supply a low frequency clock to said register means, a high frequency clock to said gate means and at least one intermediate frequency clock to said multiplexer means.

2. A M-sequence code generator as claimed in claim 1 wherein said multiplexer means comprises a plurality of multiplexer elements coupled together, and some of said elements are arranged in a first rank which receives said signals from said register means and others of said multiplexer elements are connected in a second rank which receives said signals from said first rank and supplies said signals to said gate means, and said clock means supplies said elements of said first rank with a first intermediate frequency clock and said elements of said second rank with a second intermediate frequency of a higher frequency than said first intermediate frequency clock.