System for high speed serial video signal transmission using DC-balanced coding
First Claim
1. A method of high speed digital video signal transmission comprising the steps of:
- encoding a first sequence of n bit data words into n+m bit data characters and encoding control data into n+m bit control characters where the n and the m are positive integers each of said data characters having a first plurality of logical transitions within a first range and each of said control characters having a second plurality of logical transitions in a second range different from said first range;
generating a serial data stream in response to said data and control characters;
transmitting said serial data stream over a communication link; and
separating received ones of said data and control characters received from said communication link on the basis of numbers of logical transitions in said received ones of said data and control characters.
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Accused Products
Abstract
A new high-speed digital interface for transmitting video information over various transmission media including terminated copper wires such as twisted-pair wires and fiber optical cable is described. The significance of this new interface is that (1) it only uses a small number of data channels with all timing and control data embedded in data transmission, (2) it uses a transition controlled binary DC balanced coding for reliable, low-power and high-speed data transmission, (3) it uses low-swing differential voltage which minimizes EMI, and (4) it can be implemented in low-cost scaleable CMOS technology as a megacell or standard IC. The high-speed digital interface incorporates a method and apparatus for producing a transition-controlled, DC-balanced sequence of characters from an input sequence of data bytes. The bits in each of the data bytes are selectively complemented in accordance with the number of logical transitions in each data byte in order to produce selectively complemented data blocks. A cumulative disparity is then determined between the logical values of different type included within ones of the selectively complemented data blocks previously encoded into characters. In addition, a current disparity in a candidate character associated with a current one of the selectively complemented data blocks being encoded is also determined. The candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of a polarity opposite to a first polarity of the cumulative disparity. Alternately, the complement of the candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of the first polarity. In a high-transition mode of operation, the bits within data blocks including less than a minimum number of logical transitions are selectively complemented so that each such selectively complemented data block includes in excess of the minimum number of logical transitions. In a low-transition mode of operation, the bits within data blocks having more than a predefined number of logical transitions are selectively complemented so that each such selectively complemented data block includes less than the maximum number of logical transitions.
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Citations
40 Claims
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1. A method of high speed digital video signal transmission comprising the steps of:
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encoding a first sequence of n bit data words into n+m bit data characters and encoding control data into n+m bit control characters where the n and the m are positive integers each of said data characters having a first plurality of logical transitions within a first range and each of said control characters having a second plurality of logical transitions in a second range different from said first range; generating a serial data stream in response to said data and control characters; transmitting said serial data stream over a communication link; and separating received ones of said data and control characters received from said communication link on the basis of numbers of logical transitions in said received ones of said data and control characters.
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2. In a digital video signal transmission system, a method of high speed data transmission comprising the steps of:
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encoding a first sequence of n bit data words into n+m bit data characters and encoding control data into n+m bit control characters where the n and the m are positive integers, each of said data characters having a first plurality of logical transitions within a first range and each of said control characters having a second plurality of logical transitions in a second range different from said first range; generating a serial data stream in response to said data and control characters; and transmitting said serial data stream over a communication link. - View Dependent Claims (3)
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4. In a digital video signal transmission system, a method of high speed data transmission comprising the steps of:
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encoding a first sequence of data words into data characters and encoding control data into control characters, each of said data characters having a first plurality of logical transitions within a first range and each of said control characters having a second plurality of logical transitions in a second range different from said first range; generating a serial data stream in response to said data and control characters; transmitting said serial data stream over a communication link; wherein said step of encoding a first sequence of data words further includes the step of selectively complementing bits in said data words in accordance with the number of logical transitions in each said data word in order to produce selectively complemented data blocks; and wherein said step of encoding further includes the steps of; determining a cumulative disparity in the number of logical values of different type included within ones of said selectively complemented data blocks previously encoded into ones of said characters; determining a current disparity in a candidate character associated with a current one of said selectively complemented data blocks being encoded; and assigning said candidate character to said current one of said selectively complemented data blocks if said current disparity is of a polarity opposite to a first polarity of said cumulative disparity, and assigning the complement of said candidate character to said current one of said selectively complemented data blocks if said current disparity is of said first polarity.
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5. A high speed digital video signal transmission system comprising:
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encoder means for encoding a first sequence of n bit data words into n+m bit data characters and for encoding control data into n+m bit control characters where the n and the m are positive integers; serial transmission means, coupled to a first end of a communication link, for transmitting a serial data stream over said communication link in response to said data and control characters; and means, coupled to a second end of said communication link, for distinguishing received ones of said data characters from received ones of said control characters on the basis of numbers of logical transitions in said received ones of said data and control characters. - View Dependent Claims (6)
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7. A high speed digital video signal transmission system comprising:
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a communication link having a first end and a second end; a video transmitter coupled to the first end of said communication link; a video receiver coupled to the second end of said communication link, said video receiver including means for distinguishing data characters received over said communication link from control characters received over said communication link on the basis of the number of logical transitions between bits of said data and control characters where the data characters and the control characters have the same number of bits. - View Dependent Claims (8)
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9. A high speed digital video signal transmission system comprising:
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a communication link having a first end and a second end, said communication link including a data line and clock line; a video transmitter coupled to a first end of said communication link; a video receiver coupled to a second end of said communication link; and video capture means operatively coupled to said clock line.
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10. A video transmitter comprising:
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data capture logic adapted to receive a plurality of input data signals and input control signals, each input signal received on a separate input line, for generating at least two subsets of the received input signals; and a plurality of signal transmission paths, at least one signal transmission path corresponding to each subset of input signals, each signal transmission path comprising; an encoder coupled to receive the corresponding subset of input signals from the data capture logic, for producing a DC balanced sequence of characters from the received subset of input signals; and a serializer coupled to receive the DC balanced sequence of characters from the encoder, for converting the DC balanced sequence of characters into a serial data stream; wherein the DC balanced sequence of characters comprises data characters and control characters, the data characters having a number of logical transitions falling within a first range and the control characters having a number of logical transitions falling within a second range different from the first range; and each encoder encodes the received data signals into data characters and encodes the received control signals into control characters where the data characters and the control characters have the same number of bits. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 20, 21)
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18. A video transmitter comprising:
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data capture logic adapted to receive a plurality of input data signals and input control signals, each input signal received on a separate input line, for generating at least two subsets of the received input signals; and a plurality of signal transmission paths, at least one signal transmission path corresponding to each subset of input signals, each signal transmission path comprising; an encoder coupled to receive the corresponding subset of input signals from the data capture logic, for producing a DC balanced sequence of characters from the received subset of input signals; and a serializer coupled to receive the DC balanced sequence of characters from the encoder, for converting the DC balanced sequence of characters into a serial data stream; and
wherein;each subset of input signals comprises a data block of input data signals, each data block including a plurality of bits; the DC balanced sequence of characters comprises data characters, each data character including a DC balanced data block; and each encoder encodes the received data blocks into DC balanced data blocks in accordance with a preferred set of data blocks, the preferred set selected from among a high-transition set of data blocks and a low-transition set of data blocks, the high-transition set comprising data blocks with at least a predetermined number of logical transitions, the low-transition set comprising data blocks with less than the predetermined number of logical transitions, the encoder comprising; a conditional alternate bit inversion (CABI) circuit for complementing every other bit in the received data block if the received data block is not in the preferred set, and not complementing said bits if the received data block is in the preferred set, to produce a selectively complemented data block; and a conditional byte inversion (CTBI) circuit coupled to receive the selectively complemented data block from the CABI circuit, for complementing the selectively complemented data block if a current disparity in the number of logical values of different type included within the selectively complemented data block and a cumulative disparity in the number of logical values of different type included within characters generated for previously received data blocks are of opposite polarities, and not complementing said data block if said disparities are of the same polarity, to produce the DC balanced data block. - View Dependent Claims (19)
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22. A video receiver comprising:
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at least two signal reception paths, each signal reception path comprising; a data recovery module adapted to receive a serial data stream, for converting the serial data stream to a DC balanced sequence of characters, where each of the characters has a same number of bits; and a decoder coupled to receive the DC balanced sequence of characters from the data recovery module, for converting the sequence of characters to a set of output signals; and panel interface logic coupled to receive the sets of output signals from the decoders, for combining the sets into a plurality of output data signals and a plurality of output control signals, each output signal transmitted on a separate output line. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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35. A high speed digital video system comprising:
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data capture logic adapted to receive a plurality of input data signals and input control signals, each input signal received on a separate input line, for generating at least two subsets of the received input signals; a plurality of signal communications paths, at least one signal communications path corresponding to each subset of input signals, each signal communications path comprising; an encoder coupled to receive the corresponding subset of input signals from the data capture logic, for producing a DC balanced sequence of characters from the received subset of input signals, where each of the characters has a same number of bits; a serializer coupled to receive the DC balanced sequence of characters from the encoder, for converting the DC balanced sequence of characters into a serial data stream and transmitting said serial data stream across a communications link; a data recovery module coupled to receive the serial data stream from the communications link, for converting the serial data stream to a DC balanced sequence of characters; and a decoder coupled to receive the DC balanced sequence of characters from the data recovery module, for converting the sequence of characters to a set of output signals, the set of output signals based on the subset of input signals; and panel interface logic coupled to receive the sets of output signals from the decoders, for combining the sets into a plurality of output data signals and a plurality of output control signals, each output signal transmitted on a separate output line. - View Dependent Claims (36, 37)
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38. A high speed digital video system comprising:
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a communications channel having a first end and a second end; a video transmitter adapted to receive a plurality of input signals and coupled to the first end of the communications channel, for producing a plurality of serial data streams from the plurality of input signals and transmitting said data streams across the communications channel, the plurality of input signals including input data signals and input control signals, each serial data stream including a DC balanced sequence of characters, each sequence of characters including data characters based on the input data signals and control characters based on the input control signals, where the data characters and the control characters both have a same number of bits; a video receiver coupled to the second end of the communications channel, for receiving the serial data streams and recovering the input signals from the received data streams, the receiver separating received data characters and control characters on the basis of number of logical transitions in said characters. - View Dependent Claims (39, 40)
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Specification