System for high speed serial video signal transmission using DC-balanced coding

• US 5,974,464 A
• Filed: 09/30/1996
• Issued: 10/26/1999
• Est. Priority Date: 10/06/1995
• Status: Expired due to Term

• Current Assignee: Nexus Display Technologies LLC (Acacia Research Corporation)
• Original Assignee: Silicon Image, Inc. (Lattice Semiconductor Corporation)
• Inventors: Shin, Yeshik, Lee, David D., Lee, Kyeongho, Kim, Sungjoon
• Primary Examiner(s): Rinehart, Mark H.
• Application Number:
  US08/723,694
• Time in Patent Office: 1,121 Days
• Field of Search: 395/200.61, 395/200.76, 341/59, 341/94, 341/58, 370/535, 370/536, 370/463
• US Class Current: 709/231
• CPC Class Codes: G09G 2370/045 using multiple communication channels, e.g. parallel and serial
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: G09G 5/008 Clock recovery
• CPC Class Codes: H04L 2007/045 Fill bit or bits, idle words
• CPC Class Codes: H04L 25/085 Arrangements for reducing interference in line transmission systems, e.g. by differential transmission
• CPC Class Codes: H04L 25/4915 using pattern inversion or substitution H04L25/4908 takes precedence
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/041 using special codes as synchronising signal
• CPC Class Codes: H04N 21/23602 Multiplexing isochronously with the video sync, e.g. according to bit-parallel or bit-serial interface formats, as SDI
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/4342 Demultiplexing isochronously with video sync, e.g. according to bit-parallel or bit-serial interface formats, as SDI
• CPC Class Codes: H04N 7/083 with signal insertion during the vertical and the horizontal blanking interval , e.g. MAC data signals
• CPC Class Codes: H04N 7/52 Systems for transmission of a pulse code modulated video signal with one or more other pulse code modulated signals, e.g. an audio signal or a synchronizing signal assembling of a multiplex stream by combining a video stream with other content or additional data, remultiplexing of multiplex streams, insertion of stuffing bits into the multiplex stream, assembling of a packetised elementary stream at server side H04N21/236; disassembling of a multiplex stream, remultiplexing of multiplex streams, extraction or processing of Service Information, disassembling of packetised elementary stream at client side H04N21/434

Abstract

A new high-speed digital interface for transmitting video information over various transmission media including terminated copper wires such as twisted-pair wires and fiber optical cable is described. The significance of this new interface is that (1) it only uses a small number of data channels with all timing and control data embedded in data transmission, (2) it uses a transition controlled binary DC balanced coding for reliable, low-power and high-speed data transmission, (3) it uses low-swing differential voltage which minimizes EMI, and (4) it can be implemented in low-cost scaleable CMOS technology as a megacell or standard IC. The high-speed digital interface incorporates a method and apparatus for producing a transition-controlled, DC-balanced sequence of characters from an input sequence of data bytes. The bits in each of the data bytes are selectively complemented in accordance with the number of logical transitions in each data byte in order to produce selectively complemented data blocks. A cumulative disparity is then determined between the logical values of different type included within ones of the selectively complemented data blocks previously encoded into characters. In addition, a current disparity in a candidate character associated with a current one of the selectively complemented data blocks being encoded is also determined. The candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of a polarity opposite to a first polarity of the cumulative disparity. Alternately, the complement of the candidate character is assigned to the current one of the selectively complemented data blocks if the current disparity is of the first polarity. In a high-transition mode of operation, the bits within data blocks including less than a minimum number of logical transitions are selectively complemented so that each such selectively complemented data block includes in excess of the minimum number of logical transitions. In a low-transition mode of operation, the bits within data blocks having more than a predefined number of logical transitions are selectively complemented so that each such selectively complemented data block includes less than the maximum number of logical transitions.

Claims

1. A method of high speed digital video signal transmission comprising the steps of:

encoding a first sequence of n bit data words into n+m bit data characters and encoding control data into n+m bit control characters where the n and the m are positive integers each of said data characters having a first plurality of logical transitions within a first range and each of said control characters having a second plurality of logical transitions in a second range different from said first range;

generating a serial data stream in response to said data and control characters;

transmitting said serial data stream over a communication link; and

separating received ones of said data and control characters received from said communication link on the basis of numbers of logical transitions in said received ones of said data and control characters.

2. In a digital video signal transmission system, a method of high speed data transmission comprising the steps of:

encoding a first sequence of n bit data words into n+m bit data characters and encoding control data into n+m bit control characters where the n and the m are positive integers, each of said data characters having a first plurality of logical transitions within a first range and each of said control characters having a second plurality of logical transitions in a second range different from said first range;

generating a serial data stream in response to said data and control characters; and

transmitting said serial data stream over a communication link.

3. The method of claim 2 wherein said step of encoding a first sequence of data words further includes the step of selectively complementing bits in said data words in accordance with the number of logical transitions in each said data word in order to produce selectively complemented data blocks.

4. In a digital video signal transmission system, a method of high speed data transmission comprising the steps of:

encoding a first sequence of data words into data characters and encoding control data into control characters, each of said data characters having a first plurality of logical transitions within a first range and each of said control characters having a second plurality of logical transitions in a second range different from said first range;

generating a serial data stream in response to said data and control characters;

transmitting said serial data stream over a communication link;

wherein said step of encoding a first sequence of data words further includes the step of selectively complementing bits in said data words in accordance with the number of logical transitions in each said data word in order to produce selectively complemented data blocks; and

wherein said step of encoding further includes the steps of;

determining a cumulative disparity in the number of logical values of different type included within ones of said selectively complemented data blocks previously encoded into ones of said characters;

determining a current disparity in a candidate character associated with a current one of said selectively complemented data blocks being encoded; and

assigning said candidate character to said current one of said selectively complemented data blocks if said current disparity is of a polarity opposite to a first polarity of said cumulative disparity, and assigning the complement of said candidate character to said current one of said selectively complemented data blocks if said current disparity is of said first polarity.

5. A high speed digital video signal transmission system comprising:

encoder means for encoding a first sequence of n bit data words into n+m bit data characters and for encoding control data into n+m bit control characters where the n and the m are positive integers;

serial transmission means, coupled to a first end of a communication link, for transmitting a serial data stream over said communication link in response to said data and control characters; and

means, coupled to a second end of said communication link, for distinguishing received ones of said data characters from received ones of said control characters on the basis of numbers of logical transitions in said received ones of said data and control characters.

6. The system of claim 5 wherein said encoder means includes means for encoding each of said data characters having a first plurality of logical transitions within a first range and each of said control characters having a second plurality of logical transitions in a second range.

7. A high speed digital video signal transmission system comprising:

a communication link having a first end and a second end;

a video transmitter coupled to the first end of said communication link;

a video receiver coupled to the second end of said communication link, said video receiver including means for distinguishing data characters received over said communication link from control characters received over said communication link on the basis of the number of logical transitions between bits of said data and control characters where the data characters and the control characters have the same number of bits.

8. The system of claim 7 further including:

video capture means for providing captured video information to said video transmitter, and

means for synchronizing timing between said video capture means and said video transmitter.

9. A high speed digital video signal transmission system comprising:

a communication link having a first end and a second end, said communication link including a data line and clock line;

a video transmitter coupled to a first end of said communication link;

a video receiver coupled to a second end of said communication link; and

video capture means operatively coupled to said clock line.

10. A video transmitter comprising:

data capture logic adapted to receive a plurality of input data signals and input control signals, each input signal received on a separate input line, for generating at least two subsets of the received input signals; and

a plurality of signal transmission paths, at least one signal transmission path corresponding to each subset of input signals, each signal transmission path comprising;

an encoder coupled to receive the corresponding subset of input signals from the data capture logic, for producing a DC balanced sequence of characters from the received subset of input signals; and

a serializer coupled to receive the DC balanced sequence of characters from the encoder, for converting the DC balanced sequence of characters into a serial data stream;

wherein the DC balanced sequence of characters comprises data characters and control characters, the data characters having a number of logical transitions falling within a first range and the control characters having a number of logical transitions falling within a second range different from the first range; and

each encoder encodes the received data signals into data characters and encodes the received control signals into control characters where the data characters and the control characters have the same number of bits.

11. The transmitter of claim 10 wherein the first and second ranges are selected from among a high-transition range and a low-transition range, the high-transition range being at least a predetermined number, the low-transition range being less than the predetermined number.

12. The transmitter of claim 10 wherein:

the input data signals comprise the red, green, and blue components of a video signal; and

the at least two subsets of received input signals comprise a first subset including the red component, a second subset including the green component, and a third subset including the blue component.

13. The transmitter of claim 12 wherein:

the received input control signals comprise six bits, including a horizontal sync and a vertical sync signal of one bit each;

each of the red, green, and blue components comprises eight bits; and

each subset of received input signals further includes two bits of the six bits of received input control signals.

14. The transmitter of claim 13 wherein:

each character comprises ten bits, including a DC balanced block of eight bits; and

each encoder encodes the eight bits of the red, green, or blue component as a DC balanced block with less than four logical transitions, and encodes the two bits of received input control signals as a DC balanced block with four or more logical transitions.

15. The transmitter of claim 13 wherein:

each character comprises ten bits, including a DC balanced block of eight bits; and

each encoder encodes the eight bits of the red, green, or blue component as a DC balanced block with four or more logical transitions; and

encodes the two bits of received input control signals as a DC balanced block with less than four logical transitions.

16. The transmitter of claim 12 wherein:

each of the red, green, and blue components comprises a fixed number of bits;

each character includes a DC balanced block with the fixed number of bits; and

each encoder encodes the fixed number of bits of the red, green, or blue component as a DC balanced block with less than a predetermined number of logical transitions, and encodes the received input control signals as a DC balanced block with not less than the predetermined number of logical transitions.

17. The transmitter of claim 12 wherein:

each of the red, green, and blue components comprises a fixed number of bits;

each character includes a DC balanced block with the fixed number of bits; and

each encoder encodes the fixed number of bits of the red, green, or blue component as a DC balanced block with not less than a predetermined number of logical transitions, and encodes the received input control signals as a DC balanced block with less than the predetermined number of logical transitions.

20. The transmitter of claim 10 further comprising a clock transmitter adapted to receive an input clock and coupled to send internal clocks to the encoders, for generating the internal clocks from the input clock.

21. The transmitter of claim 20 wherein a frequency of the internal clocks is an integer multiple of a frequency of the input clock.

18. A video transmitter comprising:

data capture logic adapted to receive a plurality of input data signals and input control signals, each input signal received on a separate input line, for generating at least two subsets of the received input signals; and

a plurality of signal transmission paths, at least one signal transmission path corresponding to each subset of input signals, each signal transmission path comprising;

an encoder coupled to receive the corresponding subset of input signals from the data capture logic, for producing a DC balanced sequence of characters from the received subset of input signals; and

a serializer coupled to receive the DC balanced sequence of characters from the encoder, for converting the DC balanced sequence of characters into a serial data stream; and

wherein;

each subset of input signals comprises a data block of input data signals, each data block including a plurality of bits;

the DC balanced sequence of characters comprises data characters, each data character including a DC balanced data block; and

each encoder encodes the received data blocks into DC balanced data blocks in accordance with a preferred set of data blocks, the preferred set selected from among a high-transition set of data blocks and a low-transition set of data blocks, the high-transition set comprising data blocks with at least a predetermined number of logical transitions, the low-transition set comprising data blocks with less than the predetermined number of logical transitions, the encoder comprising;

a conditional alternate bit inversion (CABI) circuit for complementing every other bit in the received data block if the received data block is not in the preferred set, and not complementing said bits if the received data block is in the preferred set, to produce a selectively complemented data block; and

a conditional byte inversion (CTBI) circuit coupled to receive the selectively complemented data block from the CABI circuit, for complementing the selectively complemented data block if a current disparity in the number of logical values of different type included within the selectively complemented data block and a cumulative disparity in the number of logical values of different type included within characters generated for previously received data blocks are of opposite polarities, and not complementing said data block if said disparities are of the same polarity, to produce the DC balanced data block.

19. The transmitter of claim 18 wherein:

the CABI circuit further generates a first bit indicating whether every other bit of the received data block has been complemented;

the CTBI circuit further generates a second bit indicating whether the selectively complemented data block has been complemented; and

each data character further includes the first bit and the second bit.

22. A video receiver comprising:

at least two signal reception paths, each signal reception path comprising;

a data recovery module adapted to receive a serial data stream, for converting the serial data stream to a DC balanced sequence of characters, where each of the characters has a same number of bits; and

a decoder coupled to receive the DC balanced sequence of characters from the data recovery module, for converting the sequence of characters to a set of output signals; and

panel interface logic coupled to receive the sets of output signals from the decoders, for combining the sets into a plurality of output data signals and a plurality of output control signals, each output signal transmitted on a separate output line.

23. The receiver of claim 22 wherein:

the DC balanced sequence of characters comprises data characters and control characters, the data characters having a number of logical transitions falling within a first range and the control characters having a number of logical transitions falling within a second range different from the first range; and

each decoder converts the received data characters into data signals and converts the received control characters into control signals, the data and control characters separated on the basis of number of logical transitions in said characters.

24. The receiver of claim 23 wherein the first and second ranges are selected from among a high-transition range and a low-transition range, the high-transition range being at least a predetermined number, the low-transition range being less than the predetermined number.

25. The receiver of claim 22 wherein:

the output data signals comprise the red, green, and blue components of a video signal; and

the sets of output signals comprise a first set including the red component, a second set including the green component, and a third set including the blue component.

26. The receiver of claim 25 wherein:

the output control signals comprise six bits, including a HSYNC and a VSYNC signal of one bit each;

each of the red, green, and blue components comprises eight bits; and

each set of output signals further includes two bits of the six bits of output control signals.

27. The receiver of claim 25 wherein:

each of the red, green, and blue components comprises a fixed number of bits;

each character includes a DC balanced block with the fixed number of bits; and

each decoder converts a DC balanced block with less than a predetermined number of logical transitions to a red, green, or blue component, and converts a DC balanced block with not less than the predetermined number of logical transitions to an output control signal.

28. The receiver of claim 25 wherein:

each of the red, green, and blue components comprises a fixed number of bits;

each character includes a DC balanced block with the fixed number of bits; and

each decoder converts a DC balanced block with not less than a predetermined number of logical transitions to a red, green, or blue component, and converts a DC balanced block with less than the predetermined number of logical transitions to an output control signal.

29. The receiver of claim 22 wherein:

the DC balanced sequence of characters comprises data characters, each data character comprising a DC balanced data block, each DC balanced data block comprising a selectively complemented data block or its complement, each selectively complemented data block comprising a data block or a data block in which every other bit has been complemented;

each set of output signals comprises the data block, each data block including a plurality of bits; and

each decoder converts the received DC balanced data blocks into data blocks.

30. The receiver of claim 29 wherein the data recovery module comprises a synchronization module adapted to receive the serial data stream, for determining the frame boundary pointer based on the received data stream, the frame boundary pointer indicating a location of a character within the data stream.

31. The receiver of claim 30 wherein the synchronization module further comprises:

a plurality of latches adapted to receive the data stream, for storing a portion of the data stream corresponding in length to more than two characters; and

combinatorial logic coupled to receive the stored data stream from the latches, for combining the stored data stream to produce the frame boundary pointer.

32. The receiver of claim 29 wherein:

each character further comprises a first bit and a second bit, each first bit indicating whether each selectively complemented data block comprises the data block or the data block in which every other bit has been complemented, and each second bit indicating whether each DC balanced data block comprises the selectively complemented data block or its complement; and

the decoder further comprises combinatorial logic for combining the first bit, the second bit, and the DC balanced data block to produce the data block corresponding to the character.

33. The receiver of claim 22 further comprising a clock receiver adapted to receive an external clock and coupled to send internal clocks to the data recovery modules, for generating the internal clocks from the external clock.

34. The receiver of claim 33 wherein a frequency of the internal clocks is an integer multiple of a frequency of the external clock.

35. A high speed digital video system comprising:

data capture logic adapted to receive a plurality of input data signals and input control signals, each input signal received on a separate input line, for generating at least two subsets of the received input signals;

a plurality of signal communications paths, at least one signal communications path corresponding to each subset of input signals, each signal communications path comprising;

an encoder coupled to receive the corresponding subset of input signals from the data capture logic, for producing a DC balanced sequence of characters from the received subset of input signals, where each of the characters has a same number of bits;

a serializer coupled to receive the DC balanced sequence of characters from the encoder, for converting the DC balanced sequence of characters into a serial data stream and transmitting said serial data stream across a communications link;

a data recovery module coupled to receive the serial data stream from the communications link, for converting the serial data stream to a DC balanced sequence of characters; and

a decoder coupled to receive the DC balanced sequence of characters from the data recovery module, for converting the sequence of characters to a set of output signals, the set of output signals based on the subset of input signals; and

panel interface logic coupled to receive the sets of output signals from the decoders, for combining the sets into a plurality of output data signals and a plurality of output control signals, each output signal transmitted on a separate output line.

36. The system of claim 35 wherein:

the DC balanced sequence of characters comprises data characters and control characters, the data characters having a number of logical transitions falling within a first range and the control characters having a number of logical transitions falling within a second range different from the first range;

each encoder encodes the received data signals into data characters and encodes the received control signals into control characters; and

each decoder converts the received data characters into data signals and converts the received control characters into control signals, the data and control characters separated on the basis of number of logical transitions in said characters.

37. The system of claim 35 wherein:

the input data signals comprise the red, green, and blue components of a video signal; and

the at least two subsets of received input signals comprise a first subset including the red component, a second subset including the green component, and a third subset including the blue component.

38. A high speed digital video system comprising:

a communications channel having a first end and a second end;

a video transmitter adapted to receive a plurality of input signals and coupled to the first end of the communications channel, for producing a plurality of serial data streams from the plurality of input signals and transmitting said data streams across the communications channel, the plurality of input signals including input data signals and input control signals, each serial data stream including a DC balanced sequence of characters, each sequence of characters including data characters based on the input data signals and control characters based on the input control signals, where the data characters and the control characters both have a same number of bits;

a video receiver coupled to the second end of the communications channel, for receiving the serial data streams and recovering the input signals from the received data streams, the receiver separating received data characters and control characters on the basis of number of logical transitions in said characters.

39. The system of claim 38 further comprising a video capture device coupled to the second end of the communications channel, for capturing video and for transmitting the captured video across the communications channel to the video transmitter.

40. The system of claim 39 further comprising:

a clock transmitter adapted to receive an input clock, coupled to send an internal clock to the video transmitter, and coupled to the first end of the communications channel, for generating the internal clock from the input clock and for transmitting the input clock across the communications channel; and

a clock receiver coupled to the second end of the communications channel and coupled to send an internal clock to the video receiver and to the video capture device, for receiving the input clock from the communications channel and for generating the internal clock from the input clock.