Computer system having distributed compression and decompression logic for compressed data movement

• US 5,974,471 A
• Filed: 07/19/1996
• Issued: 10/26/1999
• Est. Priority Date: 07/19/1996
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Belt, Steve
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): ELISCA, PIERRE E
• Application Number:
  US08/684,701
• Time in Patent Office: 1,194 Days
• Field of Search: 395/821, 395/822, 395/825, 395/882, 395/200.68, 395/200.76, 395/200.77, 395/888
• US Class Current: 710/1
• CPC Class Codes: H03M 7/30 Compression speech analysis-synthesis for redundancy reduction G10L19/00; for image communication H04N; Expansion; Suppression of unnecessary data, e.g. redundancy reduction

Abstract

A computer system having distributed compression and decompression logic for compressed data movement within the computer system. This provides increased efficiency and reduced bus bandwidth requirements. The computer system includes various standard components, including a CPU, chip set logic, main memory, one or more expansion buses, and various peripheral devices coupled to the expansion buses. Various devices may be connected to the PCI bus, including graphics accelerator hardware, audio logic, a hard drive, and a network interface card, and other multimedia devices, as desired. In the preferred embodiment, the bridge logic and/or memory controller, one or more of the multimedia devices, the hard drive, and the network interface controller each includes compression/decompression (codec) logic which performs compression and decompression operations. Thus, when a device desires to perform a transfer on the bus, the codec in the device preferably compresses the data before transferring the data onto the bus. The receiving or destination device includes codec logic which receives the compressed data and decompresses the data, and the decompressed data is then used or stored by the device. Thus, the majority of data transfers on the bus are compressed data transfers, i.e., comprise transfers of compressed data. This optimizes or reduces the required bus transfer bandwidth.

Claims

1. A computer system which includes distributed compression/decompression (codec) logic for improved data transfers, comprising:

a CPU;

a main memory coupled to the CPU which stores data accessible by the CPU;

a chip set logic coupled to the CPU, and a memory bus;

an expansion bus coupled to the chipset logic, wherein the expansion bus is adapted for transferring data;

a plurality of peripheral devices coupled to the expansion bus and configured to transfer data on the expansion bus, wherein each of said plurality of peripheral devices includes compression/decompression (codec) logic for compressing data prior to transferring data onto the expansion bus, wherein said codec logic in each of said plurality of peripheral devices operates to receive compressed data transferred on said expansion bus and operates to decompress said received compressed data for use by the respective peripheral device.

2. The computer system of claim 1, further comprising:

a memory controller coupled to the main memory for controlling transfers to or from the main memory, wherein the memory controller includes codec logic for compressing data prior to transferring data onto the expansion bus.

3. The computer system of claim 2, wherein the codec logic comprised in the memory controller receives compressed data transferred on said expansion bus and operates to decompress said received compressed data and store said decompressed data in the main memory.

4. The computer system of claim 1, wherein each of said plurality of peripheral devices includes codec detection logic for determining if a destination device includes codec logic.

5. The computer system of claim 1, wherein at least one of said plurality of peripheral devices comprises video logic for performing video operations.

6. The computer system of claim 1, wherein at least one of said plurality of peripheral devices comprises audio logic for performing audio operations.

7. The computer system of claim 1, wherein at least one of said plurality of peripheral devices comprises a network interface controller for coupling to a network, wherein the network interface controller performs network data transfer functions.

8. The computer system of claim 1, wherein at least one of said plurality of peripheral devices comprises a hard disk device for storing data.

9. The computer system of claim 1, wherein each of said codecs in said plurality of peripheral devices implements a lossless compression algorithm.

10. The computer system of claim 1, wherein said expansion bus comprises the Peripheral Component Interconnect (PCI) bus.

11. A computer system, comprising:

a CPU coupled to a CPU local bus;

a chipset coupled to the CPU local bus and to main memory, wherein said chipset interfaces to a peripheral local bus, and wherein the chipset comprises a memory controller and compression/decompression logic for compressing data prior to transferring data onto the peripheral local bus; and

a plurality of peripheral devices coupled to the peripheral local bus and configured to transfer data on the peripheral local bus, wherein each of said plurality of peripheral devices includes compression/decompression logic for compressing data prior to transferring data onto the peripheral local bus.

12. The computer system of claim 11, wherein the memory controller retrieves uncompressed data from main memory and the compression/decompression logic comprised within the chipset compresses the uncompressed retrieved data prior to transfer across the peripheral local bus to one of the plurality of peripheral devices.

13. The computer system of claim 11, wherein the memory controller retrieves compressed data from main memory and the chipset transfers the compressed retrieved data across the peripheral local bus to one of the plurality of peripheral devices.

14. The computer system of claim 11, wherein data transfers from the CPU to one of the peripheral devices are compressed by the compression/decompression logic within the chipset prior to transfer across the peripheral local bus.

15. The computer system of claim 11, wherein data transfers from one of the peripheral devices to the CPU are compressed by the compression/decompression logic within the transferring peripheral device prior to transfer across the peripheral local bus and decompressed by the compression/decompression logic within the chipset prior to transfer to the CPU.

16. The computer system of claim 11, wherein one of said peripheral devices comprises a network interface controller for transferring data to another computer on a network, wherein the compression/decompression logic comprised within the network interface controller receives compressed data and decompresses the compressed data prior to transfer across the network.

17. The computer system of claim 11, wherein one of said peripheral devices comprises a network interface controller for transferring data to another computer on a network, wherein the network interface controller receives compressed data and transfers the compressed data across the network.

18. The computer system of claim 11, wherein each compression/decompression logic in each of the plurality of peripheral devices maintains a data structure which indicates which of the other devices in the computer system include compression/decompression logic.

19. The computer system of claim 11, wherein the compression/decompression logic within the chipset maintains a data structure which indicates which of the other devices in the computer system include compression/decompression logic.

20. The computer system of claim 19, wherein the chipset only transfers compressed data to devices which also include compression/decompression logic.

21. The computer system of claim 11, wherein the chipset polls a destination device prior to transferring data to determine if the destination device includes compression/decompression logic so that the chipset transfers compressed data only to devices that include compression/decompression logic.

22. The computer system of claim 11, further comprising system Plug and Play information, wherein information about which device in the computer system includes compression/decompression logic is incorporated in the system Plug and Play information.