Enabling mirror, nonmirror and partial mirror cache modes in a dual cache system

• US 5,974,506 A
• Filed: 06/28/1996
• Issued: 10/26/1999
• Est. Priority Date: 06/28/1996
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Fava, Thomas F., Sicola, Stephen J., Lubbers, Clark E., Elkington, Susan G., Umland, Wayne H.
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): TZENG, FRED
• Application Number:
  US08/671,153
• Time in Patent Office: 1,215 Days
• Field of Search: 395/467, 395/445, 395/182.04, 395/182.03, 395/440, 395/183.12, 395/447, 395/456, 711/149, 711/118, 711/113, 711/120, 711/129
• US Class Current: 711/120
• CPC Class Codes: G06F 12/0871 Allocation or management of cache space
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/286 Mirrored cache memory
• CPC Class Codes: G11C 29/74 using duplex memories, i.e. using dual copies

Abstract

A cache memory system is enabled into one of a plurality of cache modes in a cache memory system in a computer. The cache memory system has a first controller and two cache memories, the cache memories are partitioned into quadrants with two quadrants in each cache memory. A cache mode detector in the first controller detects a mirror cache mode set for the cache memory system. An address enabler in the first controller enables access to first pair of quadrants, one quadrant in each cache memory, in response to detection of a mirror cache mode. A second controller follows the cache mode set by the cache mode detector and has an address enabler. The address enabler in the second controller enables access to both quadrants in one cache memory in a non-mirror cache mode, and enables the access to a second pair of quadrants, one quadrant in each cache memory, in response to detection of a mirror cache mode by said cache mode detector.

Claims

1. A method for operating between a non-mirror cache mode and one or more mirror cache modes in a cache memory system, the cache memory system having a controller, a first cache memory and a second cache memory, comprising the computer implemented steps of:

detecting by the controller a cache mode to be used by the cache memory system;

dividing each of the cache memories into two mirror portions upon detection of one of the mirror cache modes; and

simultaneously writing the same data by the controller to one of the mirror portions in the first cache memory and one of the mirror portions in the second cache memory.

2. The method of claim 1 wherein the cache mode detected is non-mirror cache mode further comprising the steps of:

writing data by the controller to one of the cache memories.

3. The method of claim 1 wherein the cache mode detected is mirror cache mode further comprising the steps of:

dividing the entire first cache memory into two mirror portions and the entire second cache memory into two mirror portions.

4. The method of claim 1 wherein the cache mode detected is partial mirror cache mode further comprising the steps of:

dividing each of the cache memories into two mirror portions and one non-mirror portion;

simultaneously writing by the controller the same data to a mirror portion in the first cache memory and a mirror portion in the second controller; and

writing by the controller data to the non-mirror portion in one of the cache memories.

5. The method of claim 1 and in addition:

detecting by a second controller the cache mode to be used by the cache memory system.

6. The method of claim 5 wherein the cache mode detected is non-mirror cache mode and further comprising:

writing data by the controller to one of the cache memories; and

writing another data by the second controller to the other cache memory.

7. The method of claim 5 wherein the cache mode detected is mirror cache mode further comprising:

dividing the entire first cache memory into two mirror portions and the entire second cache memory into two mirror portions; and

simultaneously writing another same data to the other mirror portion of the first cache memory and the other mirror portion of the second cache memory.

8. The method of claim 5 wherein the cache mode is partial mirror cache mode:

dividing each of the cache memories into two mirror portions and one non-mirror portion;

simultaneously writing by the controller the same data to a mirror portion in the first cache memory and a mirror portion in the second controller;

simultaneously writing by the second controller the same data to another mirror portion in the first cache memory and another mirror portion in the second controller;

writing by the controller data to the non-mirror portion in one of the cache memories; and

writing by the second controller data to the non-mirror portion in the other cache memory.

9. The method of claim 5 further comprising the steps of:

first testing pages in the non-mirror portion of the cache memories; and

putting free pages detected by the first testing step into a non-mirror pool.

10. The method of claim 5 further comprising the steps of:

second testing pages in the mirror portions of the cache memories; and

putting free pages detected by the second testing step into a mirror pool.

11. Apparatus for operating between a non-mirror cache mode and one or more mirror cache modes in a cache memory system comprising:

a first cache memory and a second cache memory; and

a controller, such controller comprising;

a cache mode detector logic for detecting and setting the cache mode for the cache memory system;

a cache division logic for dividing each of the first cache memory and the second cache memory into two mirror portions upon detection of one of the mirror cache modes; and

a memory write control logic for simultaneously writing the same data by the controller to one of the mirror portions in the first cache memory and one of the mirror portions in the second cache memory.

12. The apparatus of claim 11 and in addition:

a second controller, such second controller comprising;

a cache mode detector logic for detecting the cache mode set by the controller; and

a memory write control logic for simultaneously writing the same data by the second controller to the other mirror portion in a first cache memory and the other mirror portion in the second cache memory.

13. The apparatus of claim 12 wherein the cache mode detector logic detecting mirror cache mode:

the cache division logic dividing each of the entire first cache and the entire second cache into two mirror portions.

14. The Apparatus of claim 12 wherein the cache mode detection logic detecting non-mirror cache mode:

the memory write control logic in the controller writing data to the first cache memory; and

the memory write control logic in the second controller writing data to the second cache memory.

15. The apparatus of claim 12 wherein the cache mode detector logic detecting partial mirror cache mode:

the cache division logic dividing each of the first and second cache memories into two mirror portions and one non-mirror portion;

the memory write control logic in the controller writing other data to the non-mirror portion in the first or the second cache memory; and

the memory write control logic in the second controller simultaneously writing second same data to another mirror portion in the first cache memory and another mirror portion in the second cache memory and writing second other data to the other non-mirror portion in the first or the second cache memory.

16. A method for operating between a non-mirror cache mode and one or more mirror cache modes in a cache memory system, the cache memory system having, a first cache memory and a second cache memory, comprising the computer implemented steps of:

detecting the cache mode to be used by the cache memory system;

dividing each of the cache memories into two mirror portions upon detection of one of the mirror cache modes; and

simultaneously writing the same data to one of the mirror portions in the first cache memory and one of the mirror portions in the second cache memory.