Optimizing a cache eviction mechanism by selectively introducing different levels of randomness into a replacement algorithm

• US 5,974,507 A
• Filed: 04/14/1997
• Issued: 10/26/1999
• Est. Priority Date: 04/14/1997
• Status: Expired due to Term

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Clark, Leo James, Arimilli, Ravi Kumar, Lewis, Jerry Don, Dodson, John Steven
• Primary Examiner(s): Cabeca, John W.
• Assistant Examiner(s): Lee, Felix B.
• Application Number:
  US08/837,512
• Time in Patent Office: 925 Days
• Field of Search: 711/133, 711/159, 711/128, 711/135, 711/136, 711/134
• US Class Current: 711/133
• CPC Class Codes: G06F 12/0848 Partitioned cache, e.g. separate instruction and operand caches
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 12/127 using additional replacement algorithms
• CPC Class Codes: G06F 2212/601 Reconfiguration of cache memory

Abstract

A method of improving operation of a cache used by a processor of a computer system by introducing a level of randomness into a replacement algorithm used by the cache in order to lessen "strides" within the cache is disclosed. Different levels of randomness may be introduced into the replacement algorithm at different times to optimize the cache for different procedures running on the processor. The level of randomness can be selectively introduced by using a basic replacement algorithm to select a subset of a congruence class, and one or more random bits are then used to select a specific cache block within the subset for eviction. The basic replacement algorithm can be a least recently used algorithm. There may be three levels of randomness for a 4-way set associative cache, and there may be four levels of randomness for an 8-way set associative cache.

Claims

1. A method of improving operation of a cache used by a processor of a computer system, comprising the steps of:

providing a cache-replacement control unit to select a cache block for eviction from among a plurality of blocks in the cache;

selectively introducing a first level of randomness into a replacement algorithm used by the cache-replacement control unit;

evicting cache blocks according to the replacement algorithm using the first level of randomness;

selectively introducing a second level of randomness into the replacement algorithm; and

evicting cache blocks according to the replacement algorithm using the second level of randomness.

2. The method of claim 1 wherein the levels of randomness are selectively introduced by using a basic replacement algorithm to select a subset of a congruence class, and one or more random bits are used to select a specific cache block within the subset for eviction.

3. The method of claim 1 wherein said steps of selectively introducing the levels of randomness into the replacement algorithm selects the levels from among at least three different levels of randomness.

4. The method of claim 1 wherein said steps of selectively introducing the levels of randomness into the replacement algorithm selects the levels from among exactly four different levels of randomness.

5. The method of claim 1 wherein the replacement algorithm includes a least recently used algorithm.

6. The method of claim 3 wherein the second level of randomness is selected to optimize evictions from strides occurring in the cache.

7. The method of claim 3 wherein:

the replacement algorithm includes a non-random algorithm and a random algorithm;

a plurality of replacement control bits are used by the replacement algorithm; and

the number of such replacement control bits is equal to the maximum number of bits required to effectuate the at least three different levels of randomness using different combinations of the non-random algorithm and the random algorithm.

8. The method of claim 7 wherein:

the non-random algorithm is a least recently used algorithm;

the cache is n-way associative; and

the number of replacement control bits is equal to n-1.

9. A computer system comprising:

a processor;

a memory device;

a cache connected to said processor and said memory device, having a plurality of cache blocks for storing memory blocks corresponding to addresses of said memory device; and

a cache-replacement control unit having means for selecting a cache block for eviction from among a plurality of blocks in the cache, including means for selectively introducing at least two different levels of randomness into a replacement algorithm used by said cache-replacement control unit.

10. The computer system of claim 9 wherein said cache-replacement control unit includes means for changing said levels of randomness introduced into said replacement algorithm to optimize evictions from strides occurring in said cache.

11. The computer system of claim 9 wherein said levels of randomness are selectively introduced by using a basic replacement algorithm to select a subset of a congruence class, and one or more random bits are used to select a specific cache block within the subset for eviction.

12. The computer system of claim 9 wherein said levels of randomness are selected from among at least three different levels of randomness.

13. The computer system of claim 9 wherein said levels of randomness are selected from among exactly four different levels of randomness.

14. The computer system of claim 9 wherein said replacement algorithm includes a least recently used algorithm.

15. The computer system of claim 12 wherein:

said replacement algorithm includes a non-random algorithm and a random algorithm;

a plurality of replacement control bits are used by said replacement algorithm; and

the number of such replacement control bits is equal to the maximum number of bits required to effectuate said at least three different levels of randomness using different combinations of said non-random algorithm and said random algorithm.

16. The computer system of claim 15 wherein:

said non-random algorithm is a least recently used algorithm;

said cache is n-way associative; and

said number of replacement control bits is equal to n-1.

17. A computer system comprising:

a processor;

a memory device;

a cache connected to said processor and said memory device, having a plurality of cache blocks for storing memory blocks corresponding to addresses of said memory device; and

a cache-replacement control unit having means for selecting a cache block for eviction from among a plurality of blocks in the cache, including means for selectively introducing a level of randomness into a replacement algorithm used by said cache-replacement control unit, wherein said level of randomness is selectively introduced by using a basic replacement algorithm to select a subset of a congruence class, and one or more random bits are used to select a specific cache block within the subset for eviction.