Cache memory system and method for automatically locking cache entries to prevent selected memory items from being replaced

• US 5,974,508 A
• Filed: 10/08/1997
• Issued: 10/26/1999
• Est. Priority Date: 07/31/1992
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Maheshwari, Dinesh
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US08/947,188
• Time in Patent Office: 748 Days
• Field of Search: 711/133, 711/135, 711/136, 711/144, 711/145, 711/159, 711/160, 395/726, 395/733, 395/737
• US Class Current: 711/133
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 2212/2515 being configurable for different purposes, e.g. as cache or non-cache memory

Abstract

A cache memory system has a plurality of cache entries for storing memory items staged from a memory. The cache memory system locks entries so that memory items stored therein are prevented from being replaced by newly staged memory items. Entries can be locked globally whereby more than one entry is locked. Entries can also be locked locally whereby only selected ones of the entries are locked. The cache memory system can also set or clear a representation in an entry representing that such entry is not to be replaced upon being selectively activated or deactivated by an auto-lock (automatic lock) signal. The representation is memory-mapped and can be set or cleared directly by an integer unit.

Claims

1. A single chip central processing unit (CPU) having an integer unit for generating read and write requests to an external memory, a cache memory internal to the single chip CPU for storing memory items staged from the external memory and a bus interface unit for reading and writing memory items stored in the external memory and for replacing memory items stored in the cache memory, wherein the integer unit, cache memory and bus interface unit are interconnected by a bus, the cache memory having a plurality of cache entries for storing memory items and corresponding cache entry lock bits, the single chip CPU comprising:

a memory-mapped cache/bus interface unit (BIU) control register connected to the integer unit and having a global cache lock bit selectively settable by the integer unit for indicating that all cache entries are to be locked;

a memory-mapped lock control register connected to the integer unit and having a cache entry auto lock bit selectively settable by the integer unit for indicating that individual cache entries are to be locked when accessed by the bus interface unit; and

means connected to the cache memory, the cache/BIU control register and the lock control register, for locking all cache entries by selectively disabling replacement of all memory items stored therein by the bus interface unit while the global cache lock bit in the memory-mapped cache/BIU control register is set, and for automatically locking individual cache entries by setting the corresponding cache entry lock bits in the individual cache entries, thereby selectively disabling replacement of individual memory items stored therein, when he individual cache entries are subsequently accessed by the bus interface unit while the cache entry auto lock bit in the memory-mapped lock control register is set.

2. A single chip CPU as in claim 1 wherein each cache entry further comprises a plurality of valid bits for representing that each memory item contained therein corresponds to a memory item stored in the external memory, one of the valid bits being set when a corresponding memory item in the cache memory is replaced.

3. A single chip CPU as in claim 1 wherein the cache memory further comprises a plurality of least recently used bits, each least recently used bit representing that a corresponding cache entry that was least recently used will be the first to be replaced, each least recently used bit corresponding to one of the cache entries, one of the least recently used bits being set when a corresponding memory item in the cache memory is replaced.

4. In a computer system having a central processing unit and an external memory, the central processing unit having an integer unit for generating read and write requests and at least one cache memory system internal to the central processing unit for storing memory items staged from the external memory, each cache memory system comprising:

a memory-mapped cache/bus interface unit (BIU) control register having a global cache lock bit selectively settable by the integer unit;

a memory-mapped lock control register having a cache entry auto lock bit selectively settable by the integer unit;

a cache having a plurality of cache entries for storing the memory items staged from the external memory and corresponding cache entry lock bits;

a bus interface unit coupled to the integer unit and the cache by a first bus and coupled to the external memory by a second bus for replacing a memory item stored in the external memory in response to a write request and for replacing a memory item stored in one of the cache entries with a new memory item from the external memory in response to a read request; and

locking means coupled to the cache, the memory-mapped cache/BIU control register and the memory-mapped lock control register, for locking all cache entries by selectively disabling replacement of all memory items stored therein by the bus interface unit while the global lock bit in the memory-mapped cache/BIU control register is set, and for automatically locking individual cache entries by setting the corresponding cache entry lock bits in the individual cache entries, thereby selectively disabling replacement of individual memory items stored therein, when the individual cache entries are subsequently accessed by the bus interface unit while the cache entry auto lock bit is set in the lock control register.

5. A computer system as in claim 4, wherein each cache entry further includes a plurality of valid bits for representing that each memory item contained therein corresponds to a memory item in the external memory, whereby if a cache entry is already allocated for a new memory item, the bus interface unit sets the valid bit corresponding thereto, otherwise the bus interface unit allocates a new cache entry, sets the valid bit corresponding the new memory item and clears all other valid bits in the new cache entry.

6. A computer system as in claim 4 further comprising:

a lock control save register located in the central processing unit for saving the contents of the memory-mapped lock control register in response to an external interrupt or a hardware trap and for restoring those contents upon termination of the external interrupt or the hardware trap.

7. A computer system as in claim 4 wherein each cache entry further comprises:

a least recently used bit for representing that the cache entries that were least recently used will be the first to be replaced, whereby the locking means sets the least recently used bit on a cache hit or whenever the bus interface unit replaces a memory item stored in a cache entry.

8. A computer system as in claim 7 wherein the cache is two-way set associative.

9. A computer system as in claim 8 wherein the cache is an instruction cache which is read-only.

10. A computer system as in claim 8 wherein the cache is a data cache which is readable and writable.

11. A method for managing a cache internal to a single chip central processing unit, comprising the steps of:

storing a plurality of memory items in a plurality of cache entries in the cache, each cache entry including a corresponding cache entry lock bit;

staging a new memory item from the external memory in response to a read request that results in a cache miss;

replacing a memory item stored in one of the cache entries with the new memory item;

setting a global lock bit in a cache/bus interface unit (BIU) control register when replacement of memory items in all cache entries is to be blocked;

preventing replacement of memory items in all cache entries in the replacing step, while the global lock bit is set in the cache/bus interface unit (BIU) control register;

setting an auto lock bit in a lock control register when replacement of memory items in individual cache entries is to be blocked; and

locking individual cache entries by preventing replacement of memory items in the individual cache entries in the replacing step, by setting the corresponding cache entry lock bits of the individual cache entries, when the individual cache entries are accessed by a bus interface unit while the auto lock bit is set in the lock control register.

12. A method as in claim 11, further comprising the step of:

setting a cache entry lock bit for an individual cache entry using the single chip central processing unit to write directly to that cache entry lock bit.

13. A method as in claim 11 further comprising the steps of:

saving the contents of the lock control register in response to an external interrupt or a hardware trap; and

restoring those contents upon termination of the external interrupt or the hardware trap.

14. A method as in claim 11, wherein the cache comprises two banks, and said method further comprises:

locking one bank in response to the global lock bit being set in the cache/BIU control register; and

accessing the other bank while the global lock bit is set and the one bank is locked.

15. A method as in claim 11, wherein each cache entry further includes a plurality of valid bits for representing that each memory item contained therein corresponds to a memory item stored in an external memory, said method further comprising the step of:

setting one of the plurality of valid bits corresponding to a new memory item if a cache entry is already allocated and clearing all other valid bits in a new cache entry if a new cache entry must be allocated for the new memory item.