Controlling SDRAM memory by using truncated burst read-modify-write memory operations

• US 5,974,514 A
• Filed: 11/12/1996
• Issued: 10/26/1999
• Est. Priority Date: 11/12/1996
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: HP Inc.
• Inventors: Andrewartha, J. Michael, Friedberg, Donald H.
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): Ellis, Kevin L.
• Application Number:
  US08/747,320
• Time in Patent Office: 1,078 Days
• Field of Search: 711/105, 711/155, 711/166, 365/230.03, 365/233, 365/233.5
• US Class Current: 711/166
• CPC Class Codes: G06F 12/0879 Burst mode

Abstract

In a computer system having SDRAM memory banks that use a full burst read-modify-write operation as the sole mode for conducting memory operations, by selectively truncating the memory operation, it is possible to simulate either a burst read operation or a burst write operation. In a truncated read operation, a full read portion of the memory operation is performed. The tag is read with the first data line and is updated while the remaining lines of the burst are read. The tag is written using the write portion, but then the burst operation is aborted or truncated by issuing a precharge command to abort the write after the first line of the write is completed. This saves three clock periods out of a cycle of seventeen clock periods. A truncated write operation is similar to the read operation. A full burst read is started to retrieve the tag, which is stored to the first line, but the burst is truncated after the first line has been read. A full burst write operation is started immediately after the tag read, with the last lines of the data being written first. The tag data in the first line is being updated while the last three lines are being written. Then the cycle wraps around to write the first data line, including the tag, on the last cycle of the burst write.

Claims

1. A method for truncating a read portion of a read-modify-write memory operation, the memory operation being performed on a plurality of memory lines, a first memory line of the plurality of memory lines having tag data which describes a current state of data stored in the remaining memory lines, the method comprising the steps of:

issuing an activation command to initiate the memory operation;

issuing a read command;

reading the first memory line;

asserting a mask signal to block reading of the remaining memory lines;

updating the tag data which was read from the first memory line;

issuing a write command;

writing the remaining memory lines;

writing the first memory line with the updated tag data after the step of writing the remaining memory lines; and

issuing a precharge command to complete the memory operation.

2. A method for truncating a write portion of a read-modify-write memory operation, the memory operation is performed on a memory cache of a plurality of memory lines, a first memory line of the plurality of memory lines has tag data which describes a current state of data stored in the remaining memory lines, the method comprising the steps of:

issuing an activation command to initiate the memory operation;

issuing a read command;

reading the first memory line;

reading the remaining memory lines;

updating the tag data which was read from the first memory line;

issuing a write command;

writing the first memory line with the updated tag data after the step of reading the remaining memory lines;

asserting a mask signal to block writing of a second memory line of the plurality of memory lines; and

issuing a precharge command after the step of asserting a mask signal to truncate the memory operation and block the writing of the remaining lines.

3. A method for truncating a read portion of a read-modify-write memory operation, the memory operation being performed on a memory cache of a plurality of memory lines equal to the burst length of a particular memory, a first memory line of the plurality of memory lines having tag data which describes a current state of data stored in the remaining memory lines, the method comprising the steps of:

reading the first memory line;

asserting a mask signal to block reading of the remaining memory lines;

updating the tag data which was read from the first memory line;

writing the remaining memory lines; and

writing the first memory line with the updated tag data after the step of writing the remaining memory lines.

4. The method of claim 3, wherein:

the method for truncating the memory operation shortens the memory operation by a number of clock cycles, whereby the number of clock cycles is equal to the burst length minus one.

5. The method of claim 3, wherein:

the plurality of memory lines is four memory lines;

the first memory line comprises 8 bytes of tag data, and 2 bytes of data; and

each of the three remaining memory lines comprises 10 bytes of data.

6. The method of claim 5, wherein:

each memory line further comprises one byte of error correction code.

7. The method of claim 6, wherein:

each memory line is formed from a plurality of SDRAMs.

8. A method for truncating a write portion of a read-modify-write memory operation, the memory operation is performed on a memory cache of a plurality of memory lines equal to the burst length of a particular memory, a first memory line of the plurality of memory lines has tag data which describes a current state of data stored in the remaining memory lines, the method comprising the steps of:

reading the first memory line;

reading the remaining memory lines;

updating the tag data which was read from the first memory line;

writing the first memory line with the updated tag data after the step of reading the remaining memory lines;

asserting a mask signal to block writing of a second memory line of the plurality of memory lines; and

issuing a precharge command after the step of asserting a mask signal to truncate the memory operation and block the writing of the remaining lines.

9. The method of claim 8, wherein:

the method for truncating the memory operation shortens the memory operation by a number of clock cycles, whereby the number of clock cycles is equal to the burst length minus one.

10. The method of claim 9, wherein:

the plurality of memory lines is four memory lines;

the first memory line comprises 8 bytes of tag data, and 2 bytes of data; and

each of the three remaining memory lines comprises 10 bytes of data.

11. The method of claim 10, wherein:

each memory line further comprises one byte of error correction code.

12. The method of claim 11, wherein:

each memory line is formed from a plurality of SDRAMs.

13. A computer system having SDRAM memory chips that use a full burst read-modify-write operation as a mode for conducting memory operations, the computer system comprises:

means for issuing commands to the memory banks; and

means for selectively truncating the memory operation to simulate either a burst read operation or a burst write operation, as directed by the processor.

14. The computer system of claim 13, wherein:

the full burst read-modify-write operation is the sole and only mode for conducting memory operations.

15. The computer system of claim 13, wherein a plurality of memory lines form a cache line, a first memory line of the cache line has tag data which describes a current state of data stored in the remaining memory lines of that cache line, and the means for selectively truncating the memory operation is directed to simulate a burst read operation of the cache line by truncating the write portion of the operation, the means for selectively truncating the memory operation including:

means for asserting of a DQM mask signal after writing the first line; and

means for issuing a precharge command on a next clock cycle to truncate the remaining memory lines of the burst.

16. The computer system of claim 15, wherein:

the means for selectively truncating the memory operation shortens the memory operation by a number of clock cycles, whereby the number of clock cycles is equal to the burst length minus one.

17. The computer system of claim 15, wherein:

a number of clock cycles between reading the first memory line and writing the first memory line of the truncated memory operation is equal to a number of clock cycles between reading the first memory line and writing the first memory line in the full burst read-modify-write operation.

18. The computer system of claim 13, wherein a plurality of memory lines form a cache line, a first memory line of the cache line has tag data which describes a current state of data stored in the remaining memory lines of that cache line, and the means for selectively truncating the memory operation is directed to simulate a burst write operation of the cache line by truncating the read portion of the operation, the means for selectively truncating the memory operation including:

means for asserting a DQM mask signal after reading the first memory line;

means for issuing a write command on a next possible clock cycle after asserting the DQM signal; and

means for writing the first memory line the last cycle of the write portion of the memory operation.

19. The computer system of claim 18, wherein:

the means for selectively truncating the memory operation shortens the memory operation by a number of clock cycles, whereby the number of clock cycles is equal to the burst length minus one.

20. The computer system of claim 18, wherein:

a number of clock cycles between reading the first memory line and writing the first memory line of the truncated memory operation is equal to a number of clock cycles between reading the first memory line and writing the first memory line in the full burst read-modify-write operation.

21. The computer system of claim 13, wherein:

the plurality of memory lines is four memory lines;

the first memory line comprises 8 bytes of tag data, and 2 bytes of data; and

each of the three remaining memory lines comprises 10 bytes of data.

22. The computer system of claim 21, wherein:

each memory line further comprises one byte of error correction code.

23. The computer system of claim 22, wherein:

each memory line is formed from a plurality of SDRAMs.

24. A method for shortening the memory operation cycle in a processor system using SDRAM and using tag data to describe a current state of data stored in the SDRAM, the method comprising the steps of:

issuing a burst activate command to the SDRAM where the burst command is to effect several identified lines of the SDRAM within the burst cycle;

updating the tag data;

activating data within the burst cycle with respect to a certain number of the burst command identified lines of the SDRAM; and

selectively inhibiting activation within the burst cycle with respect to a certain number of the burst command identified lines of the SDRAM.

25. The method set forth in claim 24 wherein said selectively inhibiting step includes the step of:

asserting the DQM input of the SDRAM.

26. The method set forth in claim 24 further comprising the steps of:

cycling through all preset operations of each burst cycle without regard to whether or not activation with respect to certain lines is inhibited.

27. The method set forth in claim 24 wherein activation can be either a read or a write operation.

28. The method set forth in claim 24 wherein the activated lines are one and the inhibited lines are the remainder of the identified lines in the burst cycle.

29. The method set forth in claim 28 wherein said one activated line is the first line of the identified lines.

30. A method for shortening the memory operation cycle in a SDRAM memory system in which blocks of data are stored in a block spanning several lines of the memory and where tag information is associated with each of such data blocks, the method comprising the steps of:

activating a read-modify-write burst cycle with respect to a selected data block, where the burst cycle would require t clock periods to execute the full cycle; and

inhibiting selected memory line activations, where the number of lines that are inhibited is 1 so as to reduce the number of burst cycle clock periods to t-1.

31. The method set forth in claim 30, wherein said inhibiting selected memory line activations step includes the step of:

asserting a DQM input of the SDRAM memory system.