Apparatus and method for signal processing
First Claim
1. An associative signal processing apparatus for processing a plurality of samples of an incoming signal in parallel, the apparatus comprising:
- (a) an array of processors, each processor including a multiplicity of associative memory cells, said memory cells being operative to perform;
(i) compare operations, in parallel, on the plurality of samples of the incoming signal; and
(ii) write operations, in parallel, on the plurality of samples of the incoming signal; and
(b) an I/O buffer register including a multiplicity of associative memory cells, said register being operative to;
(i) input the plurality of samples of the incoming signal to said array of processors in parallel by having said I/O buffer register memory cells perform at least one associative compare operation and said array memory cells perform at least one associative write operation; and
(ii) receive, in parallel, a plurality of processed samples from said array of processors by having said array memory cells perform at least one associative compare operation and said I/O buffer register memory cells perform at least one write operation.
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Accused Products
Abstract
An associative signal processing apparatus for processing a plurality of samples of an incoming signal in parallel, the apparatus comprising: (a) an array of processors, each processor including a multiplicity of associative memory cells, the memory cells being operative to perform: (i) compare operations, in parallel, on the plurality of samples of the incoming signal; and (ii) write operations, in parallel, on the plurality of samples of the incoming signal; and (b) an I/O buffer register including a multiplicity of associative memory cells, the register being operative to: (i) input the plurality of samples of the incoming signal to the array of processors in parallel by having the I/O buffer register memory cells perform at least one associative compare operation and the array memory cells perform at least one associative write operation; and (ii) receive, in parallel, a plurality of processed samples from the array of processors by having the array memory cells perform at least one associative compare operation and the I/O buffer register memory cells perform at least one write operation.
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Citations
18 Claims
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1. An associative signal processing apparatus for processing a plurality of samples of an incoming signal in parallel, the apparatus comprising:
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(a) an array of processors, each processor including a multiplicity of associative memory cells, said memory cells being operative to perform; (i) compare operations, in parallel, on the plurality of samples of the incoming signal; and (ii) write operations, in parallel, on the plurality of samples of the incoming signal; and (b) an I/O buffer register including a multiplicity of associative memory cells, said register being operative to; (i) input the plurality of samples of the incoming signal to said array of processors in parallel by having said I/O buffer register memory cells perform at least one associative compare operation and said array memory cells perform at least one associative write operation; and (ii) receive, in parallel, a plurality of processed samples from said array of processors by having said array memory cells perform at least one associative compare operation and said I/O buffer register memory cells perform at least one write operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. An associative signal processing apparatus for processing a plurality of samples of an incoming signal in parallel, the apparatus comprising:
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(a) an array of processors, each processor including a multiplicity of associative memory cells, said memory cells being operative to perform; (i) compare operations, in parallel, on the plurality of samples of the incoming signal; and (ii) write operations, in parallel, on the plurality of samples of the incoming signal; (b) a register array including at least one register operative to; (i) store, in parallel, responders arriving from said associative memory cells in a plurality of said processors; and (ii) provide communication, within a single cycle, between a plurality of pairs of non-adjacent processors in said array of processors, and (c) an image correction system whereby; (i) a multiplicity of pixels from a distorted image are provided to a respective multiplicity of said associative memory cells; (ii) a transformation for an output of said image to compensate for said distortion is provided; and (iii) said transformation is executed in parallel for a plurality of said pixels via said register array.
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14. A method for processing a distorted image, the distorted image including a plurality of pixels, the method comprising the steps of:
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(a) providing an array of processors, each processor including a multiplicity of associative memory cells, said memory cells being operative to perform; (i) compare operations, in parallel, on at least a portion of the plurality of pixels; and (ii) write operations, in parallel, on at least a portion of the plurality of pixels; (b) providing a register array including at least one register operative to; (i) store responders arriving from said associative memory cells in a plurality of said processors; and (ii) provide communication, within a single cycle, between a plurality of pairs of non-adjacent processors in said array of processors; (c) providing each of the plurality of pixels to at least one of said processors; and (d) transforming at least a portion of the plurality of pixels in parallel to compensate for a distortion of the distorted image, by arranging, in parallel, in a plurality of said processors, at least two of the pixels in a single processor via said register array, and by performing in parallel, compare and write operations on a plurality of said pairs of pixels. - View Dependent Claims (15, 16, 17, 18)
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Specification