Integrated PCI buffer controller and XOR function circuit

• US 5,974,530 A
• Filed: 10/02/1997
• Issued: 10/26/1999
• Est. Priority Date: 03/15/1996
• Status: Expired due to Term

• Current Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Original Assignee: Adaptec Incorporated (Steel Partners Holdings LP)
• Inventors: Young, B. Arlen
• Primary Examiner(s): An, Meng-Ai T.
• Assistant Examiner(s): Davis, Jr., Walter D.
• Application Number:
  US08/942,373
• Time in Patent Office: 754 Days
• Field of Search: 712/43, 710/104, 710/131, 710/1, 710/101, 711/112, 714/48, 714/801
• US Class Current: 712/43
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

An integrated buffer controller and data function circuit includes a data function circuit that is controlled by addresses supplied to the circuit. The integrated buffer controller and data function circuit has a bus interface that is used to connect the circuit to a bus on which one or more host adapters are connected so that both the host adapters and a host computer can transfer data to and from the circuit, and supply addresses to control operation of this data function circuit. A data channel in the integrated buffer controller and data function circuit connects the bus interface to a buffer memory controller. The buffer memory controller has a buffer memory port that includes a data port, a memory address port, and a memory control port. A buffer memory is connected to the buffer memory port. A data function circuit in the buffer memory controller is coupled to a data function enable output line. The data function circuit is selectively connected to the data port by a signal on the data function enable output line. In one embodiment, the data channel is a slave data channel. The integrated buffer controller and data function circuit also includes a master data channel connecting the bus interface to the memory controller. The master data channel includes a DMA controller connected to the bus interface, and a master first-in-first-out memory circuit connected between the DMA controller and the buffer memory controller.

Claims

1. An integrated buffer controller and data function circuit comprising:

a bus interface circuit including an address decode circuit having a data function enable output line,

wherein said address decode circuit generates an inactive signal on said data function enable output line for a first set of addresses; and

said address decode circuit generates an active signal on data function enable output line for a second set of addresses different from said first set of addresses;

a buffer memory controller comprising;

a buffer memory port including a data port, a memory address port; and

a data function circuit coupled to said data function enable output line, and selectively connected to said data port; and

a data channel having a first end connected to said bus interface circuit and a second end connected to said memory controller

wherein in response to an inactive signal on said data function enable output line, said memory controller circuit couples said second end of said data channel to said data port; and

in response to an active signal on said data function enable output line, said buffer memory controller couples said data function circuit to said data port.

2. An integrated buffer controller and data function circuit as in claim 1 wherein said data channel is a slave data channel.

3. An integrated buffer controller and data function circuit as in claim 2 further comprising:

a master data channel connecting said bus interface circuit to said memory controller.

4. An integrated buffer controller and data function circuit as in claim 3 wherein said master data channel further comprises:

a DMA controller connected to said bus interface circuit.

5. An integrated buffer controller and data function circuit as in claim 4 wherein said master data channel further comprises:

a master first-in-first-out memory circuit connected between said DMA controller and said buffer memory controller.

6. An integrated buffer controller and data function circuit as in claim 2 wherein said slave data channel further comprises:

a slave first-in-first-out memory circuit connected between said bus interface circuit and said buffer memory controller.

7. An integrated buffer controller and data function circuit as in claim 1 further comprising:

a sequencer connected to said buffer memory controller.

8. An integrated buffer controller and data function circuit as in claim 1 wherein said buffer memory port is connected to a memory external to said integrated buffer controller and data function circuit.

9. An integrated buffer controller and data function circuit as in claim 1 wherein said bus interface circuit is connected to a PCI bus.

10. An integrated buffer controller and data function circuit as in claim 1 wherein said data function circuit is an Exclusive OR function circuit.

11. An integrated buffer controller and data function circuit comprising:

a bus interface circuit including an address decode circuit having a data function enable output line,

wherein said address decode circuit generates an inactive signal on said data function enable output line for a first set of addresses; and

said address decode circuit generates an active signal on data function enable output line for a second set of addresses different from said first set of addresses;

a buffer memory controller comprising;

a buffer memory port including a data port, a memory address port; and

a data function circuit coupled to said data function enable output line, and selectively connected to said data port;

a slave data channel having a first end connected to said bus interface circuit and a second end connected to said memory controller

wherein in response to an inactive signal on said data function enable output line, said memory controller circuit couples said second end of said data channel to said data port; and

in response to an active signal on said data function enable output line, said buffer memory controller couples said data function circuit to said data port; and

a master data channel connecting said bus interface circuit to said memory controller.

12. An integrated buffer controller and data function circuit as in claim 11 wherein said master data channel further comprises:

a DMA controller connected to said bus interface circuit.

13. An integrated buffer controller and data function circuit as in claim 12 wherein said master data channel further comprises:

a master first-in-first-out memory circuit connected between said DMA controller and said buffer memory controller.

14. An integrated buffer controller and data function circuit as in claim 11 further comprising:

a sequencer connected to said buffer memory controller.

15. An integrated buffer controller and data function circuit as in claim 11 wherein said slave data channel further comprises:

a slave first-in-first-out memory circuit connected between said bus interface circuit and said buffer memory controller.

16. An integrated buffer controller and data function circuit as in claim 11 wherein said buffer memory port is connected to a memory external to said integrated buffer controller and data function circuit.

17. An integrated buffer controller and data function circuit as in claim 11 wherein said bus interface circuit is connected to a PCI bus.

18. An integrated buffer controller and data function circuit as in claim 11 wherein said data function circuit is an Exclusive OR function circuit.

19. An integrated buffer controller and data function circuit comprising:

a bus interface circuit including an address decode circuit having a data function enable output line,

wherein said address decode circuit generates an inactive signal on said data function enable output line for a first set of addresses; and

said address decode circuit generates an active signal on data function enable output line for a second set of addresses different from said first set of addresses;

a buffer memory controller comprising;

a buffer memory port including a data port, a memory address port; and

a data function circuit coupled to said data function enable output line, and selectively connected to said data port;

a slave data channel having a first end connected to said bus interface circuit and a second end connected to said memory controller

wherein in response to an inactive signal on said data function enable output line, said memory controller circuit couples said second end of said data channel to said data port; and

in response to an active signal on said data function enable output line, said buffer memory controller couples said data function circuit to said data port; and

a master data channel connecting said bus interface circuit to said memory controller wherein said master data channel further comprises;

a DMA controller connected to said bus interface circuit; and

a master first-in-first-out memory circuit connected between said DMA controller and said buffer memory controller; and

a sequencer connected to said buffer memory controller and said DMA controller.

20. An integrated buffer controller and data function circuit as in claim 19 wherein said slave data channel further comprises:

a slave first-in-first-out memory circuit connected between said bus interface circuit and said buffer memory controller.

21. An integrated buffer controller and data function circuit as in claim 19 wherein said buffer memory port is connected to a memory external to said integrated buffer controller and data function circuit.

23. An integrated buffer controller and data function circuit as in claim 19 wherein said data function circuit is an Exclusive OR function circuit.

22. An integrated buffer controller and data function circuit as in claim 19wherein said bus interface circuit is connected to a PCI bus.