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Integrated PCI buffer controller and XOR function circuit

  • US 5,974,530 A
  • Filed: 10/02/1997
  • Issued: 10/26/1999
  • Est. Priority Date: 03/15/1996
  • Status: Expired due to Term
First Claim
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1. An integrated buffer controller and data function circuit comprising:

  • a bus interface circuit including an address decode circuit having a data function enable output line,wherein said address decode circuit generates an inactive signal on said data function enable output line for a first set of addresses; and

    said address decode circuit generates an active signal on data function enable output line for a second set of addresses different from said first set of addresses;

    a buffer memory controller comprising;

    a buffer memory port including a data port, a memory address port; and

    a data function circuit coupled to said data function enable output line, and selectively connected to said data port; and

    a data channel having a first end connected to said bus interface circuit and a second end connected to said memory controllerwherein in response to an inactive signal on said data function enable output line, said memory controller circuit couples said second end of said data channel to said data port; and

    in response to an active signal on said data function enable output line, said buffer memory controller couples said data function circuit to said data port.

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