Method of fabricating a fully self-aligned TFT-LCD

• US 5,976,902 A
• Filed: 08/03/1998
• Issued: 11/02/1999
• Est. Priority Date: 08/03/1998
• Status: Expired due to Term

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Shih, Hsueh-Feng
• Primary Examiner(s): WILCZEWSKI, MARY A
• Application Number:
  US09/127,847
• Time in Patent Office: 456 Days
• Field of Search: 438/30, 438/158, 438/FOR 155, 438/FOR 136, 438/FOR 200, 438/FOR 211, 257/59, 257/72
• US Class Current: 438/30
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate

Abstract

An ITO layer and a first metal layer is patterned on a glass substrate. A first silicon nitride layer, a silicon layer and a second silicon nitride layer are formed on the substrate. A back-side exposure is introduced using the gate electrodes as a mask. The second silicon nitride layer that is not covered by a positive photoresist is etched. A heavily doped silicon layer is formed over the substrate. A negative photoresist is formed over the heavily doped silicon layer. Then, a further back-side exposure is employed. The heavily doped silicon layer over the etched second silicon nitride layer is removed. Via holes are created to expose a portion of the first metal layer. A second metal layer and a third metal layer are respectively formed. Next, a thermal annealing is performed for forming silicide. Subsequently, a third metal layer and the second metal layer are patterned. Then, the island pattern is defined. Subsequently, a passivation layer formed of silicon nitride layer is deposited on the island pattern.

Claims

1. A method of forming a thin film transistor (TFT) on a glass substrate, said method comprising:

forming an indium tin oxide (ITO) on said glass substrate;

forming a first metal layer on said ITO layer;

patterning said first metal layer, said ITO layer to form a gate electrode of said TFT;

forming a first silicon nitride layer on said gate electrode and on said glass substrate;

forming a silicon layer on said first silicon nitride layer;

forming a second silicon nitride layer on said silicon layer;

forming a first positive photoresist on said second silicon nitride layer;

exposing said first positive photoresist from a back side of said glass substrate using said gate electrode as a mask and removing exposed portion of said first positive photoresist;

etching said second silicon nitride layer using said first positive photoresist as a mask, thereby leaving residual portion of said second silicon nitride layer over said gate electrode;

removing said first positive photoresist;

forming a doped silicon layer along a surface of said silicon layer and said residual portion of said second silicon nitride layer;

forming a negative photoresist on said doped silicon layer;

exposing said negative photoresist from said back side of said glass substrate using said gate electrode as a mask and then removing unexposed portion of said negative photoresist;

etching said doped silicon layer using said negative photoresist as a mask, thereby exposing said residual portion of said second silicon nitride layer;

removing said negative photoresist;

patterning a second positive photoresist on said doped silicon layer to define a contact region;

etching said residual portion of said second silicon nitride layer, said silicon layer and said first silicon nitride layer to from a contact hole;

forming a second metal layer on said doped silicon layer, said residual portion of said second silicon nitride layer and in said contact hole;

forming a third metal layer on said second metal layer;

performing a thermal process to form silicide at the interface between said doped silicon layer and said second metal layer;

patterning a third positive photoresist on said third metal layer;

etching said third metal layer using said third positive photoresist as a mask;

removing said third positive photoresist;

etching said second metal layer using said etched third metal layer as a mask, thereby forming source and drain regions;

etching said silicon layer and doped silicon layer to define an island pattern; and

forming a passivation layer over said glass substrate.

2. The method of claim 1, wherein said first metal layer is selected from a group consisting of chromium (Cr), tungsten (W), titanium (Ti), tantalum (Ta) and molybdenum (Mo).

3. The method of claim 1, wherein said silicon layer comprises amorphous silicon layer.

4. The method of claim 1, wherein said doped silicon layer comprises silicon layer having n conductive type dopant.

5. The method of claim 4, wherein said n conductive type dopant comprises phosphorus.

6. The method of claim 4, wherein said n conductive type dopant comprises arsenic.

7. The method of claim 1, wherein said second silicon nitride layer is etched using said first positive photoresist as a mask by buffer hydrofluoric acid.

8. The method of claim 1, wherein said second silicon nitride layer is etched using said first positive photoresist as a mask by dry etching containing SF₆, O₂.

9. The method of claim 1, wherein said second metal layer comprises Cr.

10. The method of claim 1, wherein said second metal layer comprises Mo.

11. The method of claim 1, wherein said third metal layer comprises Al.

12. The method of claim 1, wherein said third metal layer comprises Al--Nd.

13. The method of claim 1, wherein said thermal process is performed in ambient containing air.

14. The method of claim 1, wherein said thermal process is performed in ambient containing N₂.

15. The method of claim 1, wherein said thermal process is performed at a temperature about 200 to 300 degrees centigrade.

16. The method of claim 1, wherein said thermal process is performed about 30-90 minutes.