Memory cell and method for producing the memory cell

• US 5,976,932 A
• Filed: 06/30/1997
• Issued: 11/02/1999
• Est. Priority Date: 06/28/1996
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG
• Original Assignee: Siemens AG
• Inventors: Kerber, Martin
• Primary Examiner(s): CRANE, SARA W
• Application Number:
  US08/884,770
• Time in Patent Office: 855 Days
• Field of Search: 257/314, 257/315, 257/316, 257/321, 257/322, 438/264, 438/258, 438/594, 438/257, 438/265
• US Class Current: 438/257
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling

Abstract

A memory cell and a method for producing the memory cell have a plurality of structured layers disposed on a semiconducting base body and an exactly defined overlap region of a first doped region and a floating gate layer. A control gate layer is disposed approximately without any overlap over the first doped region. The memory cell can be programmed with the aid of the Fowler-Nordheim tunnel effect.

Claims

1. A method for producing a memory cell, which comprises:

a) applying an oxide layer on a main surface of a semiconducting base body;

b) applying a floating gate layer on the oxide layer;

c) applying a dielectric on the floating gate layer;

d) applying a control gate layer on the dielectric defining edges of the control gate layer and defining a region of the main surface not covered by the control gate layer;

e) applying a covering layer on the control gate layer;

f) doping two doped regions of a first conduction type into the semiconducting base body using a photomask;

g) removing the photomask;

h) producing two spacers each on a respective one of the edges of the control gate layer;

i) removing the spacer on one of the edges of the control gate layer leaving a remaining spacer and defining a region of the main surface not covered by the remaining spacer;

j) removing the dielectric and the floating gate layer from the regions of the main surface not covered by the control gate layer and not covered by the remaining spacer; and

k) removing the remaining spacer.

2. The method for producing a memory cell according to claim 1, which comprises:

overlapping at least one of the doped regions with at least one first partial region of the floating gate layer; and

overlapping at least one of the doped regions with at least one second partial region of the control gate layer being smaller than the at least one first partial region.

3. The method for producing a memory cell according to claim 1, which comprises:

defining a given distance between the edges of the control gate layer; and

defining edges of the floating gate layer at a distance therebetween less than the given distance.

4. A method for producing a memory cell, which comprises:

a) applying an oxide layer on a main surface of a semiconducting base body;

b) applying a floating gate layer on the oxide layer;

c) applying a dielectric on the floating gate layer;

d) applying a control gate layer on the dielectric defining edges of the control gate layer and defining a region of the main surface not covered by the control gate layer;

e) applying a covering layer on the control gate layer;

f) doping two doped regions of a first conduction type into the semiconducting base body using a photomask;

g) removing the photomask;

h) producing two spacers each on a respective one of the edges of the control gate layer defining a region of the main surface not covered by the spacers;

i) removing the dielectric and the floating gate layer from the regions of the main surface not covered by the control gate layer and not covered by the spacers; and

j) removing the spacers.

5. A method for producing a memory cell, which comprises:

a) applying an oxide layer on a main surface of a semiconducting base body;

b) applying a floating gate layer on the oxide layer;

c) applying a dielectric on the floating gate layer;

d) applying a control gate layer on the dielectric defining edges of the control gate layer and defining a region of the main surface not covered by the control gate layer;

e) doping two doped regions of a first conduction type into the semiconducting base body using a photomask;

f) removing the photomask;

g) producing two spacers each on a respective one of the edges of the control gate layer;

h) removing the spacer on one of the edges of the control gate layer leaving a remaining spacer and defining a region of the main surface not covered by the remaining spacer;

i) removing the dielectric and the floating gate layer from the regions of the main surface not covered by the control gate layer and not covered by the remaining spacer; and

j) removing the remaining spacer.