Silicon carbide semiconductor device

• US 5,976,936 A
• Filed: 07/15/1997
• Issued: 11/02/1999
• Est. Priority Date: 09/06/1995
• Status: Expired due to Term

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Tokura, Norihito, Miyajima, Takeshi, Fuma, Hiroo, Hara, Kazukuni
• Primary Examiner(s): Booth, Richard A
• Assistant Examiner(s): LEBENTRITT, MICHAEL
• Application Number:
  US08/893,221
• Time in Patent Office: 840 Days
• Field of Search: 438/268, 438/981, 438/275
• US Class Current: 438/268
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: Y10S 438/981 Utilizing varying dielectric thickness

Abstract

A silicon carbide semiconductor device having a high blocking voltage, low loss, and a low threshold voltage is provided. An n⁺ type silicon carbide semiconductor substrate 1, an n^- type silicon carbide semiconductor substrate 2, and a p type silicon carbide semiconductor layer 3 are successively laminated on top of one another. An n⁺ type source region 6 is formed in a predetermined region of the surface in the p type silicon carbide semiconductor layer 3, and a trench 9 is formed so as to extend through the n⁺ type source region 6 and the p type silicon carbide semiconductor layer 3 into the n^- type silicon carbide semiconductor layer 2. A thin-film semiconductor layer (n type or p type) 11a is extendedly provided on the surface of the n⁺ type source region 6, the p type silicon carbide semiconductor layer 3, and the n^- type silicon carbide semiconductor layer 2 in the side face of the trench 9.

Claims

1. A process for producing a silicon carbide semiconductor device, comprising:

a first step of laminating a first conductive type low-resistance semiconductor layer, a first conductive type high-resistance semiconductor layer, and a second conductive type first semiconductor layer in that order on top of one another to form a semiconductor substrate of a single crystal silicon carbide and forming a first conductive type semiconductor region in a predetermined region of the surface portion in the first semiconductor layer;

a second step of forming a trench extending through the semiconductor region and the first semiconductor layer into the high-resistance semiconductor layer;

a third step of forming a second semiconductor layer, formed of a single crystal silicon carbide, on at least the side face of the inner wall of the trench;

a fourth step of forming a gate oxide layer on the surface of the second semiconductor layer in the trench;

a fifth step of forming a gate electrode on the surface of the gate oxide film in the trench; and

a sixth step of forming a first electrode on the surface of the semiconductor region and optionally on the surface of the first semiconductor layer and forming a second electrode on the surface of the low-resistance semiconductor layer.

2. The process according to claim 1, wherein the silicon carbide constituting the semiconductor substrate is of the hexagonal system and the surface of the semiconductor substrate has a carbon face with a substantially (0001) face orientation.

3. The process according to claim 1, wherein, in the third step, the second semiconductor layer is formed on the surface of the first semiconductor layer and the semiconductor region and the side face and bottom of the trench and, thereafter, the second semiconductor layer on the surface of the first semiconductor layer and the semiconductor region and the bottom of the trench is thermally oxidized deeper than the second semiconductor layer on the side face of the trench to leave the second semiconductor layer on only the side face of the trench.

4. The process according to claim 1, wherein, in the third step, the second semiconductor layer is formed by epitaxial growth.

5. The process according to claim 1, wherein, in the first step, the semiconductor region is formed by epitaxial growth.

6. The process according to claim 1, wherein the second step involves the formation of the trench by dry etching and the formation and removal of an oxide layer on the inner wall of the trench, the thickness of the oxide layer on the side face being smaller than that of the oxide layer on the bottom.

7. The process according to claim 2, wherein, in the third step, the second semiconductor layer is formed on the inner wall of the trench by anisotropic epitaxial growth on the inner wall of the trench so that the thickness of the second semiconductor layer on the side face is larger than that of the second semiconductor layer on the bottom.

8. The process according to claim 7, wherein, in the fourth step, the gate oxide layer is formed on the inner wall of the trench by anisotropic thermal oxidation so that the thickness of the gate oxide layer on the side face is smaller than that of the gate oxide layer on the bottom face.

9. A process for producing a semiconductor device using silicon carbide, comprising the steps of:

preparing a silicon carbide substrate having a surface of a (0001) carbon face;

forming a trench on the surface of the (0001) carbon face;

forming a semiconductor layer on bottom and side surfaces of the trench; and

thermally oxidizing the semiconductor layer such that the semiconductor layer formed on the bottom surface of the trench is entirely converted to an oxide layer while the semiconductor layer formed on the side surface of the trench is partially converted to an oxide layer to leave a thinned semiconductor layer interposed between the oxide layer converted from the semiconductor layer on the side surface of the trench and the side surface of the trench.

10. A process for producing a MOS transistor, comprising the steps of:

laminating a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type to provide a semiconductor substrate composed of silicon carbide and having a surface of a (0001) carbon face of the second semiconductor layer of the second conductivity type;

forming a trench extending from the surface to the first semiconductor layer of the first conductivity type;

forming a third semiconductor layer at least on the bottom and side surfaces of the trench;

thermally oxidizing the third semiconductor layer such that the third semiconductor layer formed on the bottom surface of the trench is entirely converted to an oxide layer while the third semiconductor layer formed on the side surface of the trench is partially converted to an oxide layer as a gate oxide layer of a MOS transistor to leave a thinned third semiconductor layer as a channel region of the MOS transistor interposed between the oxide layer converted from the third semiconductor layer on the side surface of the trench and the side surface of the trench; and

forming a gate electrode in the trench.