Method of making silicon quantum wires on a substrate

• US 5,976,957 A
• Filed: 10/24/1997
• Issued: 11/02/1999
• Est. Priority Date: 10/28/1996
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Gosain, Dharam Pal, Usui, Setsuo, Nakagoe, Miyako, Westwater, Jonathan
• Primary Examiner(s): Mulpuri, Savitri
• Application Number:
  US08/956,081
• Time in Patent Office: 739 Days
• Field of Search: 438/686, 438/489, 438/478, 438/770, 438/787, 438/486, 438/503, 438/723, 438/756, 438/22, 438/28, 438/962, 257/3, 257/14, 117/12
• US Class Current: 438/478
• CPC Class Codes: B82Y 15/00 Nanotechnology for interacting, sensing or actuating, e.g. quantum dots as markers in protein assays or molecular motors
• CPC Class Codes: C30B 11/12 Vaporous components, e.g. vapour-liquid-solid-growth
• CPC Class Codes: C30B 25/005 Growth of whiskers or needles
• CPC Class Codes: C30B 25/04 Pattern deposit, e.g. by using masks
• CPC Class Codes: C30B 29/06 Silicon
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/02653 Vapour-liquid-solid growth
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: Y10S 438/962 Quantum dots and lines
• CPC Class Codes: Y10S 977/874 Probe tip array
• CPC Class Codes: Y10S 977/875 with tip detail
• CPC Class Codes: Y10S 977/879 Material

Abstract

While a silicon substrate is heated, gold is evaporated thereon at a thickness of 0.6 nm, whereby melted alloy droplets are formed on the substrate surface. Then, the silicon substrate is heated to 450°-650° C. in a silane gas atmosphere of less than 0.5 Torr. As a result, a silane gas decomposition reaction occurs with the melted alloy droplets serving as catalysts, whereby silicon wires grow on the substrate surface. Subsequently, the metal alloy droplets at the tips of the silicon wires are removed and surface portions of the silicon wires are oxidized. Resulting surface oxide films are thereafter removed. As a result, silicon quantum wires that are thinner by the thickness of the surface oxide films are obtained.

Claims

1. A manufacturing method of a quantum wire, comprising the steps of:

evaporating, on a silicon substrate, a metal to serve as a catalyst in a decomposition reaction of a silicon material gas;

growing a silicon wire on a surface of the silicon substrate by heating the silicon substrate on which the metal is evaporated in an atmosphere containing the silicon material gas and thereby decomposing the silicon material gas with the metal serving as a catalyst;

oxidizing the silicon wire thus grown to form an oxide film in a surface portion;

removing the metal at a tip of the silicon wire; and

removing the oxide film.

2. The manufacturing method according to claim 1, wherein the metal is evaporated at a thickness of 5 nm or less in the metal evaporating step.

3. The manufacturing method according to claim 1, wherein the metal is gold.

4. The manufacturing method according to claim 1, wherein the silicon material gas is at least one of a silane gas, a disilane gas, and a trisilane gas.

5. The manufacturing method according to claim 3, wherein in the silicon wire growing step the silicon substrate is heated at 450°

C. or more in an atmosphere containing the silicon material gas at less than 0.5 Torr.