Trench dram cell with vertical device and buried word lines
First Claim
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1. An integrated circuit memory cell comprising:
- a substrate;
a trench capacitor formed in said substrate and having a conductive area and a first insulating layer between the conductive area and said substrate;
a vertically stacked transistor having first, second and third stacked conductivity regions formed over said substrate, the second region being of a first conductivity type, and the first and third regions being of a second conductivity type, wherein the second region resides between said first and third regions, said vertically stacked transistor having a first vertical side and a second vertical side, wherein one of the vertical sides of the first stacked conductivity region is in contact with the conductive area of said trench capacitor;
a second insulating layer between the first stacked conductivity region and said substrate;
a third insulating layer positioned on one of the vertical sides of the second stacked conductivity region;
a word line over said third insulating layer and positioned to form a gate of said transistor; and
a bit line in contact with said third stacked conductivity region.
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Abstract
A DRAM array having trench capacitor cells of potentially 4F2 surface area (F being the photolithographic minimum feature width), and a process for fabricating such an arrays. The array has a cross-point cell layout in which a memory cell is located at the intersection of each bit line and each word line. Each cell in the array has a vertical device such as a transistor, with the source, drain, and channel regions of the transistor being formed from epitaxially grown single crystal silicon. The vertical transistor is formed above the trench capacitor.
365 Citations
42 Claims
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1. An integrated circuit memory cell comprising:
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a substrate; a trench capacitor formed in said substrate and having a conductive area and a first insulating layer between the conductive area and said substrate; a vertically stacked transistor having first, second and third stacked conductivity regions formed over said substrate, the second region being of a first conductivity type, and the first and third regions being of a second conductivity type, wherein the second region resides between said first and third regions, said vertically stacked transistor having a first vertical side and a second vertical side, wherein one of the vertical sides of the first stacked conductivity region is in contact with the conductive area of said trench capacitor; a second insulating layer between the first stacked conductivity region and said substrate; a third insulating layer positioned on one of the vertical sides of the second stacked conductivity region; a word line over said third insulating layer and positioned to form a gate of said transistor; and a bit line in contact with said third stacked conductivity region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A DRAM cell comprising:
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a vertical transistor having a first doped silicon region formed on a substrate, a second doped silicon region formed on the first doped silicon region, and a third doped silicon region formed on the second doped silicon region; a trench capacitor located below said vertical transistor in the substrate and having a doped polysilicon electrode, wherein the electrode is in contact with the first doped silicon region; an insulating layer located between said vertical transistor and the substrate; a conductive line gating the second doped silicon region; and a bit line in contact with the third doped silicon region. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29)
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30. A DRAM cell comprising:
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a vertical transistor having a first doped silicon region formed on a substrate, a second doped silicon region formed on the first doped silicon region, and a third doped silicon region formed on the second doped silicon region, wherein the second doped silicon region is of a first conductivity type, and the first and third doped silicon regions are of a second conductivity type, wherein the vertical transistor has a first and a second vertical sides; a trench capacitor located in a trench in the substrate on the first vertical side of said vertical transistor and having a doped polysilicon electrode of a second conductivity type, wherein the electrode is in contact with the first doped silicon region, and having a dielectric layer between the electrode and the substrate; a first insulating layer located between said vertical transistor and the substrate; a body line of a first conductivity type in contact with the second doped silicon region on the first vertical side of said vertical transistor; a conductive line of a second conductivity type gating the second doped silicon region on the second vertical side of said vertical transistor, wherein a second insulating layer lies between the conductive line and the second doped silicon region; and a bit line of a second conductivity type in contact with the third doped silicon region.
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31. A semiconductor memory array comprising:
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a substrate; a plurality of memory cells arranged into an array of rows and columns, wherein each memory cell comprises a trench capacitor located in the substrate and a vertical transistor having first, second and third regions located above the trench capacitor, wherein the first region of the vertical transistor adjoins the trench capacitor, each memory cell having an area of 4F2 where F is the minimum lithographic feature size; a plurality of bit lines, wherein each bit line is in contact with the third region of each vertical transistor in a respective column; and a plurality of buried word lines, wherein each word line adjoins the second region of each vertical transistor in a respective row, and is separated from the second region by an insulating layer. - View Dependent Claims (32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42)
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Specification