Apparatus and method for electrostatic discharge protection with improved current dispersion

• US 5,977,595 A
• Filed: 06/18/1997
• Issued: 11/02/1999
• Est. Priority Date: 06/27/1996
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Ham, Seog-heon
• Primary Examiner(s): Martin-Wallace, Valencia
• Assistant Examiner(s): Eckert, II, George C.
• Application Number:
  US08/878,483
• Time in Patent Office: 867 Days
• Field of Search: 257/355, 257/356, 257/357, 257/358, 257/360, 257/363, 257/365, 257/341, 257/401, 257/775
• US Class Current: 257/358
• CPC Class Codes: H01L 27/027 specially adapted to provide an electrical current path other than the field effect induced current path
• CPC Class Codes: H01L 27/0288 using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps

Abstract

The present invention relates to an apparatus and method for protecting a semiconductor device, and more particularly to an n-type metal-oxide semiconductor (NMOS) transistor with a ladder structure, used for protecting a semiconductor device from electrostatic discharge. In the present invention, a plurality of drain branches are connected by resistors, and a contact point of the well and the source/well pattern is formed only alongside the drain branch of the ladder structure which is nearest an input/output terminal of the semiconductor device. Accordingly, the current is better dispersed to all of the drain branches, thereby preventing the voltage breakdown of the transistor due to heat caused by the localization of current in the drain branch farthest from the input/output terminal.

Claims

1. An electrostatic protection transistor, the transistor comprising:

a semiconductor substrate having a well region having a first dopant type and wherein the well region is selectively diffused with a second dopant type to form a plurality of source active regions and drain active regions formed within the well region;

a gate contact having a plurality of gate branches formed independently of one another on the semiconductor substrate and disposed substantially parallel to one another such that each one of the plurality of gate branches has a first and second side wherein the first side is opposite to the second side;

a source contact formed on the semiconductor substrate and having a pattern which includes a source main line and a plurality of source branches, wherein each one of the plurality of source branches is disposed substantially perpendicular to the source main line, and further wherein each one of the plurality of source branches is further disposed along the first side of a corresponding one of the plurality of gate branches, and still further wherein each one of the plurality of source branches is connected to one of the source active regions;

a plurality of drain branches formed independently of one another on the semiconductor substrate and disposed substantially parallel to one another, wherein each one of the plurality of drain branches corresponds to one of the plurality of gate branches, and further wherein each one of the plurality of drain branches is disposed along the second side of the corresponding one of the plurality of gate branches, and still further wherein each one of the plurality of drain branches is connected to one of the drain active regions;

a plurality of resistors wherein each one of the plurality of resistors corresponds to a pair of adjacent drain branches and is coupled between the pair of adjacent drain branches; and

wherein one of the plurality of source branches is further connected to the well region.

2. The transistor of claim 1, wherein one of the plurality of drain branches is configured to be coupled to an input/output terminal of a semiconductor device.

3. The transistor of claim 2, the transistor further including a contact between one of the source branches and the well formed parallel to an adjacent drain branch.

4. The transistor of claim 3, wherein the source branch connected to the well is disposed near to the input/output terminal of the semiconductor device.

5. The transistor of claim 4, wherein the source branch connected to the well is closer to the input/output terminal of the semiconductor device than any other one of the plurality of source branches.

6. A method for dispersing current in an electrostatic protection transistor, the method comprising the steps:

disposing a gate contact having a plurality of gate branches over a semiconductor substrate;

diffusing source and drain active areas into the semiconductor substrate;

disposing a source contact having a plurality of source branches over the source active areas, such that the source branches are adjacent the gate branches;

coupling the source branches to the source active areas;

disposing a plurality of drain branches over the drain active areas, such that the drain branches are adjacent the gate branches;

coupling the drain branches to the drain active areas;

coupling the plurality of drain branches to one another with resistors;

selecting one of the source branches to be closest to an input/output terminal on the semiconductor substrate;

coupling the source branch selected to be closest to the input/output terminal to a well in the semiconductor substrate.

7. The method of claim 6, wherein the step of coupling the source branch closest to the input/output terminal to a well in the semiconductor substrate includes the step of disposing a contact region connecting the source branch selected to be closest to the input/output terminal to the well adjacent to a lengthwise axis of the source branch which is parallel to a lengthwise axis of an adjacent drain branch the step of coupling the source branch closest to the input/output terminal to a well in the semiconductor substrate includes the step of disposing a contact region connecting the source branch selected to be closest to the input/output terminal to the well adjacent to a lengthwise axis of the source branch which is parallel to a lengthwise axis of an adjacent drain branch.

8. The method of claim 6, further including the steps:

coupling the drain branches to the input/output terminal; and

coupling the source contact to a ground potential.

9. An electrostatic protection device for a semiconductor device having an input/output terminal, the electrostatic protection device comprising:

a p-type well region;

a plurality of n-type source active regions formed within the p-type well region;

a plurality of n-type drain active regions formed within the p-type well region;

a gate contact having a plurality of gate branches, the gate branches being disposed upon the p-type well region and between the source active regions and drain active regions;

a source contact having a plurality of source branches, each source branch being disposed upon and connected to one of the source active regions, and each source branch being further disposed adjacent to one of the gate branches, and wherein the source contact is coupled to a ground potential;

a plurality of independently formed drain branches, each drain branch being disposed upon and connected to one of the drain active regions, and each drain branch being further disposed adjacent to one of the gate branches, and wherein the plurality of drain branches is coupled to the input/output terminal;

a plurality of resistors, each resistor being disposed between an adjacent pair of drain branches;

wherein a one of the plurality of source branches which is closest to the input/output terminal is coupled to the p-type well region.

10. The electrostatic protection device of claim 9, wherein:

each of the plurality of gate branches is formed with a lengthwise axis, wherein the lengthwise axis of each gate branch is parallel to the lengthwise axis of each other gate branch;

each of the plurality of source branches is formed with a lengthwise axis, wherein the lengthwise axis of each source branch is parallel to the lengthwise axis of each other source branch and the lengthwise axis of each gate branch;

each of the plurality of drain branches is formed with a lengthwise axis, wherein the lengthwise axis of each drain branch is parallel to the lengthwise axis of each other drain branch and the lengthwise axis of each gate branch and each source branch; and

wherein the source branch coupled to the p-type well region is connected to the p-type well region along an axis parallel to the lengthwise axis of the source branch.