Depletion controlled isolation stage

• US 5,977,596 A
• Filed: 10/29/1998
• Issued: 11/02/1999
• Est. Priority Date: 09/30/1991
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Duvvury, Charvaka, Maki, Tatsuroh, Rountree, Robert
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): Eckert, II, George C.
• Application Number:
  US09/182,361
• Time in Patent Office: 369 Days
• Field of Search: 257/360, 257/356, 257/363, 361/56, 361/91, 361/98, 361/100, 361/101
• US Class Current: 257/363
• CPC Class Codes: H01L 27/0259 using bipolar transistors as protective elements
• CPC Class Codes: H01L 27/0288 using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps

Abstract

An input protection device is presented having a depletion controlled isolation stage. In one embodiment of the invention, a depletion controlled isolation resistor is formed between adjacent N+ diffused regions by N-well diffusion. One N+ diffused region electrically contacts an input bond pad and a primary protective device. The other N+ diffused region electrically contacts a second protective device and the internal circuit it is to protect. The depletion controlled isolation resistor limits the amount of current passing through the resistor to a safe level during an over-voltage condition. In another embodiment of the invention, a depletion controlled isolation stage includes a silicon controlled rectifier (SCR) as the primary protective device in combination with the depletion controlled isolation resistor.

Claims

1. An isolation stage de vice for protecting a circuit structure against over-voltage conditions, comprising:

a lightly doped region having a first conductivity type formed in a lightly doped substrate having a second conductivity type;

a first heavily doped region formed at an intersection of said substrate and said lightly doped region having said first conductivity type, said first heavily doped region being electrically connected to a first input node;

a second heavily doped region formed at least partially in said lightly doped region having said first conductivity type, said second heavily doped region being electrically connected to said circuit structure; and

a resistive means being electrically connected between said first heavily doped region and said second heavily doped region having a resistance responsive to the voltage between said first heavily doped region and said second heavily doped region.

2. An isolation stage device for protecting a circuit structure against over-voltage conditions, comprising:

a lightly doped region having a first conductivity type formed in a lightly doped substrate having a second conductivity type;

a first heavily doped region formed at least partially in said lightly doped region having said first conductivity type, said first heavily doped region being electrically connected to a first input node;

a primary discharge device being electrically connected to said first heavily doped region;

a second heavily doped region formed at least partially in said lightly doped region having said first conductivity type, said second heavily doped region being electrically connected to said circuit structure;

a secondary discharge device being electrically connected to said second heavily doped region; and

a resistive means being electrically connected between said first heavily doped region and said second heavily doped region having a resistance responsive to the voltage between said first heavily doped region and said second heavily doped region.

3. An integrated circuit device, comprising:

a bond pad;

a lightly doped region having a first conductivity type formed in a lightly doped substrate having a second conductivity type;

a first heavily doped region having said first conductivity type formed at least partially in said lightly doped region, said first heavily doped region being electrically connected to said bond pad;

a primary discharge device being electrically connected to said first heavily doped region;

a second heavily doped region having said first conductivity type formed in said lightly doped region, said second heavily doped region being electrically connected to said circuit structure;

a secondary discharge device being electrically connected to said second heavily doped region; and

a resistive means being electrically connected between said first heavily doped region and said second heavily doped region and having a resistance responsive to the voltage between said first heavily doped region and said second heavily doped region.

4. An integrated circuit, comprising:

a bond pad;

an internal circuit;

a lightly doped region having a first conductivity type formed in a lightly doped substrate having a second conductivity type, said lightly doped region comprising a resistive region;

a first heavily doped region having said first conductivity type formed at least partially in said lightly doped region, said first heavily doped region being electrically connected to said bond pad;

a primary device being electrically connected between said bond pad and a reference terminal;

a second heavily doped region having said first conductivity type formed at least partially in said lightly doped region, said second heavily doped region being electrically connected to said internal circuit, wherein said resistive region substantially determines a resistance between said first heavily doped region and said second heavily doped region; and

a secondary device being electrically connected between said second heavily doped region and said reference terminal.

5. An integrated circuit as in claim 4, wherein said primary device is a silicon controlled rectifier.

6. An integrated circuit as in claim 4, wherein said lightly doped region comprises an N-well region.

7. An integrated circuit as in claim 4, wherein each of said first and second heavily doped regions are elongated regions being spaced apart, said first heavily doped region being parallel to said second heavily doped region.

8. An integrated circuit as in claim 7, further comprising a third heavily doped formed at an intersection of said substrate and said lightly doped region having said first conductivity type, said third heavily doped region being elongated and spaced apart from said first heavily doped region and opposite said second heavily doped region, said third heavily doped region being parallel to said first heavily doped region.

9. An integrated circuit as in claim 8, further comprising a fourth heavily doped region having the second conductivity type and being electrically connected to said first heavily doped region, said fourth heavily doped region being elongated and formed between said first and third heavily doped regions.

10. An integrated circuit as in claim 4, wherein said primary device is a diode.

11. An integrated circuit as in claim 4, wherein said secondary device is a diode.