Highly integrated chip-on-chip packaging

• US 5,977,640 A
• Filed: 06/26/1998
• Issued: 11/02/1999
• Est. Priority Date: 06/26/1998
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Sprogis, Edmund Juris, Ference, Thomas George, Bertin, Claude Louis, Howell, Wayne John
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): THAI, LUAN C
• Application Number:
  US09/105,419
• Time in Patent Office: 494 Days
• Field of Search: 257/777, 257/778, 257/779, 257/780, 257/686, 257/738, 257/723, 361/735, 361/723, 361/743, 361/760
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/07811 : Extrinsic, i.e. with electrical conductive fillers
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA

Abstract

The advantages of the invention are realized by a chip-on-chip module having at least two fully functional chips, electrically connected together, and a chip-on-chip component connection/interconnection for electrically connecting the fully functional chips to external circuitry.

Claims

1. An apparatus comprising:

a chip-on-chip module having at least two independent chips with active regions electrically connected together, wherein said active regions of said two chips are facing each other; and

an interconnection substrate for electrically connecting said chips to external circuitry, the interconnection substrate including a first set of connection elements connected to the active regions of the chips, a second set of connection elements for connection to the external circuitry, and a substrate having conductive lines, the conductive lines connecting the first set of connection elements to the second set of connection elements;

wherein the second set of connection elements includes a first set of connectors, planar with a first backside of one of the at least two chins, and a second set of connectors, planar with a second backside of another of the at least two chips, for connecting the chip-on-chip module to a second chip-on-chip module.

2. The apparatus of claim 1, wherein the at least two chips are of different technologies.

3. The apparatus of claim 1, wherein said external circuitry is a leadframe.

4. The apparatus of claim 1, wherein the interconnection substrate is at least a same height as one of said at least two chips of said chip-on-chip module.

5. The apparatus of claim 1, wherein a plurality of the chip-on-chip modules are stackable upon one another.

6. The apparatus of claim 1, wherein the first set of connectors includes solder balls.

7. The apparatus of claim 1, wherein the second set of connectors includes metallurgical pads.

8. A chip-on-chip package comprising:

an external component;

a chip-on-chip module having at least two independent chips with active regions electrically connected together, wherein said active regions of said two chips are facing each other; and

an interconnection substrate for electrically connecting said chips and said external component, the interconnection substrate including a first set of connection elements connected to the active regions of the chips, a second set of connection elements for connection to the external component, and a substrate having conductive lines, the conductive lines connecting the first set of connection elements to the second set of connection elements;

wherein the second set of connection elements includes a first set of connectors, planar with a first backside of one of the at least two chips, and a second set of connectors, planar with a second backside of another of the at least two chips, for connecting the chip-on-chip module to a second chip-on-chip module.

9. The chip-on-chip package of claim 8, wherein the at least two chips are of different technologies.

10. The chip-on-chip package of claim 8, wherein said external component has a pluggable connection.

11. The chip-on-chip package of claim 8, wherein a plurality of the chip-on-chip modules are stackable upon one another.

12. The chip-on-chip package of claim 8, wherein the first set of connectors includes solder balls.

13. The chip-on-chip package of claim 8, wherein the second set of connectors includes metallurgical pads.