Embedded memory block with FIFO mode for programmable logic device

• US 5,977,791 A
• Filed: 04/14/1997
• Issued: 11/02/1999
• Est. Priority Date: 04/15/1996
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Veenstra, Kerry S.
• Primary Examiner(s): SANTAMAURO, JON P
• Application Number:
  US08/834,426
• Time in Patent Office: 932 Days
• Field of Search: 326/37-41
• US Class Current: 326/40
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/1776 for memories

Abstract

An programmable logic device has an enhanced embedded array block for the efficient implementation of logic functions including a random access memory and a first-in, first-out memory. A read address register and a write address register are implemented within the embedded array block. The address registers are coupled with a memory array in the embedded array block without using a resources from a programmable interconnect scheme. The first-in, first-out memory may operate as a dual-port FIFO, without cycle-sharing on the interconnect lines.

Claims

1. A configurable logic block in a programmable logic device integrated circuit comprising:

a memory array, wherein said memory array comprises a plurality of memory cells arranged in a random access memory format and address lines to address each of said plurality of memory cells;

a first register coupled to said address lines of said memory array, wherein in a FIFO mode, said configurable logic block operates as a first-in, first-out memory and said first register contains a write address;

a second register coupled to said address lines of said memory array, wherein in said FIFO mode, said second register contains a read address; and

a local interconnect having a plurality of conductors which are programmably coupled to said memory array, said first register, and said second register, wherein said first and second registers are coupled to said address lines of said memory array without passing through said local interconnect.

2. The configurable logic block of claim 1, wherein in said FIFO mode, said first register is configured as a counter and said second register is configured as a counter.

3. The configurable logic block of claim 1 wherein said address lines of said memory array further comprise:

a write address port, said write address port being coupled to said first register when in said FIFO mode; and

a read address port, said read address port being coupled to said second register when in said FIFO mode.

4. The configurable logic block of claim 1 further comprising:

an address input multiplexer, said first register being selectively coupled to said address lines of said memory array through said address input multiplexer during a write phase, and said second register being selectively coupled to said address lines of said memory array through said address input multiplexer during a read phase.

5. The configurable logic block of claim 4 wherein said local interconnect is selectively coupled to said address lines through said address input multiplexer.

6. The configurable logic block of claim 3 wherein said memory array further comprises:

a data-in port for storing data to a write address of said memory array specified in said write address lines; and

a data-out port for reading data from a read address of said memory array specified in said read address lines, wherein data is readable on said data-out port concurrently with data being stored on said data-in port.

7. The configurable logic block of claim 1 wherein said local interconnect provides control signals to said first register, said second register, and said memory array.

8. The configurable logic block of claim 7 wherein said control signals include a read enable signal, a write enable signal, a read clock, a write clock, and a reset signal.

9. The configurable logic block of claim 1 wherein said memory array is configurable with respect to a width of said memory array and a depth of said memory array.

10. The configurable logic block of claim 1 wherein a write enable input to said memory array is synchronously timed with respect to a clock signal.

11. The configurable logic block of claim 1 wherein a data input and address input to said memory array are asynchronously timed with respect to a write enable input to said memory array.

12. The configurable logic block of claim 1 wherein said first register is operable as a counter when in said FIFO mode, and as a data register in a mode other than said FIFO mode.

13. A programmable logic device comprising a plurality of configurable logic blocks as recited in claim 1, wherein said plurality of configurable logic blocks may be programmably coupled together to create a larger configurable logic block.

14. A programmable integrated circuit comprising:

an interconnect grid comprising a plurality of horizontal conductors and a plurality of vertical conductors, wherein said vertical conductors may be programmably coupled to said horizontal conductors;

a plurality of logic array blocks programmably coupled to said interconnect grid; and

an embedded array block, programmably coupled to said interconnect grid, wherein said embedded array block is configurable as a RAM in a RAM mode and a FIFO in a FIFO mode and comprises;

a memory array, wherein said memory array comprises a plurality of memory cells arranged in a random access memory format and address lines to address said memory array;

a first register coupled to said address lines of said memory array, wherein said first register stores a write address when said embedded array block is in said FIFO mode;

a second register coupled to said address lines of said memory array, wherein said second register stores a read address when said embedded array block is in said FIFO mode; and

a local interconnect, wherein said local interconnect is programmably coupled to said interconnect grid, first register and said second register, and said first register and second register are coupled to said address lines of said memory array without passing through said local interconnect.

15. The programmable integrated circuit of claim 14 wherein when said embedded array block is in said FIFO mode, said first register and said second register are operable as counters.

16. The programmable integrated circuit of claim 15 wherein when said embedded array block is in said RAM mode, said first register is configured as a D-type register.

17. The programmable integrated circuit of claim 14 wherein said address lines of said memory array further comprise:

write address lines, said write address lines being coupled to said first register when said embedded array block is in said FIFO mode; and

read address lines, said read address lines being coupled to said second register when said embedded array block is in said FIFO mode.

18. The programmable integrated circuit of claim 14 further comprising:

an address input multiplexer, wherein while said embedded array block is in said FIFO mode, said address input multiplexer selectively couples said address lines of said memory array to said first register during a write phase and to said second register during a read phase.

19. The programmable integrated circuit of claim 17 wherein said memory further comprises:

a data-in port for storing data to a write address of said FIFO specified in said write address lines; and

a data-out port for reading data from a read address of said FIFO specified in said read address lines, wherein data is readable on said data-out port concurrently with data being stored on said data-in port.

20. The programmable integrated circuit of claim 14 wherein one of said plurality of logic array blocks is configured to duplicate said first register and said second register, and to provide a status flag representative of a status of said memory array.

21. The programmable integrated circuit of claim 20 wherein said status flag is asserted when said memory array is nearly full.

22. The programmable integrated circuit of claim 14 wherein said memory array is configurable with respect to a width of said memory array and a depth of said memory array.

23. The programmable integrated circuit of claim 14 wherein said memory array is operated as a synchronous memory.

24. The programmable integrated circuit of claim 14 wherein said memory array is operated as an asynchronous memory.

25. A digital system having a programmable integrated circuit as recited in claim 14.

26. A programmable integrated circuit comprising:

an interconnect grid;

a first array block, programmably coupled to said interconnect grid;

a second array block, programmably coupled to said interconnect grid, is configurable as a RAM in a RAM mode and a FIFO in a FIFO mode, said second array block comprising;

a memory array, said memory array having a plurality of memory cells arranged in a random access memory format and address lines to address said memory array;

a first register coupled to said address lines of said memory array, said first register containing a write address when said second array block is in said FIFO mode;

a second register coupled to said address lines of said memory array, said second register containing a read address when said second array block is in said FIFO mode; and

a local interconnect, said local interconnect being programmably coupled to said interconnect grid, first register, and second register, wherein said first register and said second register are coupled to said address lines of said memory array without passing through said local interconnect.

27. The programmable integrated circuit of claim 26 wherein when said second array block is in said FIFO mode, said first register and said second register are configured as counters.

28. The programmable integrated circuit of claim 26 wherein said address lines of said memory array further comprise:

write address lines, said write address lines being coupled to said first register when said second array block is in said FIFO mode; and

read address lines, said read address lines being coupled to said second register when said second array block is in said FIFO mode.

29. The programmable integrated circuit of claim 28 wherein said memory further comprises:

a data-in port for storing data to a write address of said FIFO specified in said write address lines; and

a data-out port for reading data from a read address of said FIFO specified in said read address lines, wherein data is readable on said data-out port concurrently with data being stored on said data-in port.

30. A programmable integrated circuit comprising:

an interconnect grid comprising a plurality of horizontal conductors and a plurality of vertical conductors, wherein said vertical conductors may be programmably coupled to said horizontal conductors;

a plurality of logic array blocks programmably coupled to said interconnect grid; and

an embedded array block, programmably coupled to said interconnect grid wherein said embedded array block is configurable as a RAM in a RAM mode and a FIFO in a FIFO mode and said embedded array block comprises;

a memory array, wherein said memory array comprises a plurality of memory cells arranged in a random access memory format and address lines to address said memory array;

a first register coupled to said address lines of said memory array, wherein said first register stores a write address when said embedded array block is in said FIFO mode;

a second register coupled to said address lines of said memory array, wherein said second register stores a read address when said embedded array block is in said FIFO mode; and

a local interconnect, wherein said local interconnect is programmably coupled to said interconnect grid, first register, and second register, wherein one of said plurality of logic array blocks is configured to duplicate said first register and said second register, and to provide a status flag representative of a status of said memory array.

31. The programmable integrated circuit of claim 30 wherein when said embedded array block is in said RAM mode, said first register is configured as a D-type register.

32. The programmable integrated circuit of claim 30 wherein address lines of said memory array further comprise:

write address lines, said write address lines being coupled to said first register when said embedded array block is in said FIFO mode; and

read address lines, said read address lines being coupled to said second register when said embedded array block is in said FIFO mode.

33. The programmable integrated circuit of claim 30 further comprising:

an address input multiplexer, wherein while said embedded array block is in said FIFO mode, said address input multiplexer selectively couples said address lines of said memory array to said first register during a write phase and to said second register during a read phase.

34. The programmable integrated circuit of claim 32 wherein said memory further comprises:

a data-in port for storing data to a write address of said FIFO specified in said write address lines; and

a data-out port for reading data from a read address of said FIFO specified in said read address lines, wherein data is readable on said data-out port concurrently with data being stored on said data-in port.

35. The programmable integrated circuit of claim 30 wherein said status flag is asserted when said memory array is nearly full.

36. The programmable integrated circuit of claim 30 wherein said memory array is configurable with respect to a width of said memory array and a depth of said memory array.

37. The programmable integrated circuit of claim 30 wherein said memory array is operated as a synchronous memory.

38. The programmable integrated circuit of claim 30 wherein said memory array is operated as an asynchronous memory.

39. A digital system having a programmable integrated circuit as recited in claim 30.

40. A programmable logic integrated circuit comprising:

a programmable interconnect array;

a plurality of configurable logic blocks programmably coupled to the programmable interconnect array; and

a plurality of configurable memory blocks, programmably coupled to the programmable interconnect array, wherein a configurable memory block is operable as a random access memory in a RAM mode and a first-in, first-out memory in a FIFO mode and comprises;

a local interconnect;

a memory array comprising a read address input and write address input;

a first register coupled to the local interconnect, wherein in the FIFO mode, the first register stores a write address and is coupled to the read address input of the memory array without passing through the local interconnect; and

a second register coupled to the local interconnect, wherein in the FIFO mode, the second register stores a read address and is coupled to the write address input of the memory array without passing through the local interconnect.

41. The programmable logic integrated circuit of claim 40 wherein a configurable memory block further comprises:

a first multiplelxer coupled between the first register and the read address input of the memory array; and

a second multiplexer coupled between the second register and the write address input of the memory array.

42. The programmable logic integrated circuit of claim 41 wherein a configurable memory block further comprises:

a third register coupled to the local interconnect;

a third multiplexer selectively coupling the third register or the local interconnect to the first and second multiplexers, wherein in the RAM mode, the third multiplexer is coupled to the read and write address inputs of the memory array.

43. The programmable logic integrated circuit of claim 40 wherein the first and second registers are counters.

44. The programmable logic integrated circuit of claim 40 wherein the memory array is a dual-port memory.

45. The programmable logic integrated circuit of claim 40 wherein the memory array is a synchronous memory.

46. The programmable logic integrated circuit of claim 40 wherein the memory array is an asynchronous memory.

47. The programmable logic integrated circuit of claim 40 wherein the memory array may be organized as 256 rows of 8 bits, 512 rows of 4 bits, 1024 rows of 2 bits, or 2048 rows of 1 bit.

48. The programmable logic integrated circuit of claim 43 wherein increment inputs to the first and second registers are coupled to the local interconnect.

49. The programmable logic integrated circuit of claim 40 wherein the memory array comprises SRAM memory cells.

50. The programmable logic integrated circuit of claim 42 wherein clock inputs to the first, second, and third registers are coupled together.