Low voltage differential swing interconnect buffer circuit

• US 5,977,796 A
• Filed: 06/26/1997
• Issued: 11/02/1999
• Est. Priority Date: 06/26/1997
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Gabara, Thaddeus John
• Primary Examiner(s): Santamauro, Jon
• Assistant Examiner(s): LE, DON P
• Application Number:
  US08/882,827
• Time in Patent Office: 859 Days
• Field of Search: 326/21, 326/30, 326/83, 326/86, 326/119, 326/121, 326/125, 326/34
• US Class Current: 326/86
• CPC Class Codes: H03K 19/00384 in field effect transistor circuits
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0278 Arrangements for impedance matching
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end

Abstract

A low voltage differential swing interconnect I/O buffer within an output buffer part comprising a voltage controlled current source, voltage controlled current sink, and a current switch and an input buffer part comprising a voltage controlled resistance. The output current and input resistance of the I/O buffer is determined by biasing voltages which are generated by on-chip reference circuits and applied to the voltage controlled components of the I/O buffer. Using two input reference voltages and a single reference resistor, the reference circuits dynamically adjust the biasing voltages so that the I/O buffer maintains the required output current and input resistance for all manufacturing process, supply voltage, and chip temperature variations.

Claims

1. An integrated circuit that includes a low voltage differential swing interconnect buffer and biasing circuit for data transmission over first and second balanced transmission lines having a terminating resistor of a first resistance;

said integrated circuit connected to a reference resistance;

said interconnect buffer and basing circuit comprising;

an output buffer connected to said transmission lines and comprising a first voltage controlled current source having a first bias voltage and being connected to a first supply voltage, a first voltage controlled current sink having a second bias voltage and being connected to ground, and a current switch being connected in series between said first voltage controlled current source and said first voltage controlled current sink, said current switch controlling the direction of current flow from said output buffer and through said first and second balanced transmission lines and terminating resistor;

an input buffer comprising a first voltage controlled input resistor having a third bias voltage and a comparator for detecting the polarity of a voltage drop across said voltage controlled input resistor when input current flows through it;

a first voltage reference circuit having high and low input reference voltages and being connected to said reference resistance, said first voltage reference circuit generating said first and second bias voltages such that current from said output buffer through said first and second transmission lines generates a voltage drop across said terminating resistor substantially from said high input reference voltage to said low input reference voltage; and

a second voltage reference circuit having as an input said first and second bias voltages and at least one of said input reference voltages, said second voltage reference circuit generating said third bias voltage to bias said first voltage controlled resistor in said input buffer to a resistance substantially equal to said first resistance.

2. The circuit of claim 1, wherein said current switch comprises a first and second switch connected to a first node, and a third and fourth switch connected to a second node;

said first and third switches being connected in series and said second and fourth switches being connected in series;

said first transmission line being connected to said first and third switches, and said second transmission line being connected to said second and fourth switches;

a first current path being defined by when said first and fourth switches are conducting and said second and third switches are non-conducting; and

a second current path being defined when said first and fourth switches are non-conducting and said second and third switches are conducting.

3. The circuit of claim 2, further including a current switch control circuit having a binary data input signal and a plurality of output control signals which bias said first through fourth switches as either conducting or non-conducting to thereby select either said first current path or said second current path according to the value of said data input signal.

4. The circuit of claim 3, wherein said current switch control circuit is connected to a second supply voltage, said second supply voltage having magnitude greater than or equal to said first supply voltage.

5. The circuit of claim 2, wherein said first voltage reference circuit comprises:

a second voltage controlled current connected to said first supply voltage and a fifth switch biased in the conducting state and connected in series between said second voltage controlled current source and said reference resistor at a third node;

a second voltage controlled current sink connected to ground and a sixth switch biased in the conducting state and being connected in series between said second voltage controlled current sink and said reference resistor at a fourth node; and

a feedback circuit generating said first and second bias voltages which bias said second voltage controlled current source and said second voltage controlled current sink, respectively, such that the voltage at said third node equals said high input reference voltage and the voltage at said fourth node equals said low input reference voltage.

6. The circuit of claim 5, wherein said feedback circuit comprises:

a first operational amplifier having said first bias voltage as an output and having said high input reference voltage and the voltage at said third node as inputs, said input voltages being connected such that the magnitude of the current through said second voltage controlled current source is inversely dependent on the voltage at said third node;

a second operational amplifier having said second bias voltage as an output and having said low input reference voltage and the voltage at said fourth node as inputs, said input voltages being connected such that the magnitude of the current through said second voltage controlled current sink is dependent on the voltage at said fourth node.

7. The circuit of claim 5, further including at least one of a first capacitor connected between the output of said first operational amplifier and said fourth node and a second capacitor connected between the output of said second operational amplifier and said third node.

8. The circuit of claim 5, wherein said first resistance of said terminating resistor equals said reference resistance and said second voltage controlled current source, second voltage controlled current sink, fifth switch, and sixth switch have substantially the same operating characteristics as said first voltage controlled current source, first voltage controlled current sink, first switch, and fourth switch, respectively.

9. The circuit of claim 2, wherein said second voltage reference circuit comprises:

a second voltage controlled current source under the control of said first bias voltage and being connected to said first supply voltage;

a fifth switch biased in the conducting state and connected in series between said second voltage controlled current source and a second voltage controlled resistor at a third node;

a second voltage controlled current sink under the control of said second bias voltage and being connected to ground;

a sixth switch biased in the conducting state and being connected in series between said second voltage controlled current sink and said second voltage controlled resistor at a fourth node; and

a feedback circuit generating said third bias voltage which biases said second voltage controlled resistor such that the voltage at said third node equals said high input reference voltage and the voltage at said fourth node equals said low input reference voltage.

10. The circuit of claim 9, wherein said feedback circuit comprises an operational amplifier having said third bias voltage as an output and having as inputs said high input reference voltage and the voltage at said third node connected such that the resistance of said second voltage controlled resistor is inversely dependent on the voltage at said third node.

11. The circuit of claim 9, wherein said feedback circuit comprises an operational amplifier having as an output said third bias voltage and having as inputs said low input reference voltage and the voltage at said fourth node, said input voltages being connected such that the resistance of said second voltage controlled resistor is dependent on the voltage at said fourth node.

12. The circuit of claim 9, wherein said second voltage controlled current source, second voltage controlled current sink, second voltage controlled resistance, fifth switch, and sixth switch have substantially the same operating characteristics as said first voltage controlled current source, first voltage controlled current sink, first voltage controlled resistance, first switch, and fourth switch, respectively.

13. The circuit of claim 1, wherein said output buffer further includes a second voltage controlled resistance connected across said first and second balanced transmission lines.

14. The circuit of claim 13, wherein said second voltage controlled resistance has substantially the same operating characteristics as said first voltage controlled resistance.

15. The circuit of claim 1, wherein said input buffer further includes a hysteresis circuit between said first voltage controlled resistor and said comparator.

16. The circuit of claim 15, wherein said hysteresis circuit comprises a one-bit memory cell.

17. The circuit of claim 1, wherein said first voltage controlled resistor is connected across said first and second transmission lines.

18. The circuit of claim 17, further including a data enable circuit having a data enable signal as an input, said data enable circuit biasing said current switch in a non-conducting state to prevent current flow between said output buffer and said first and second transmission lines when said data enable signal is not active.

19. The circuit of claim 18 further including a resistance enable circuit having a resistance enable signal as an input, said resistance enable circuit biasing said first voltage controlled resistor in a high-impedance state when said resistance enable signal is not active.

20. The circuit of claim 3, wherein said first voltage controlled resistor is connected across said first and second transmission lines.

21. The circuit of claim 20, wherein said current switch control circuit further includes a data enable signal as an input, said current control circuit biasing said first through fourth switches as non-conducting when said data enable signal is not active.

22. The circuit of claim 21 further including a resistance enable circuit having a resistance enable signal as an input, said resistance enable circuit biasing said first voltage controlled resistor in a high-impedance state when said resistance enable signal is not active.

23. An integrated circuit that includes a differential swing interconnect I/O buffer comprising an output buffer and an input buffer;

said input buffer having first and second inputs and comprising a first variable input resistor having resistance determined by a resistor control voltage and being connected between said first and second inputs and to an input detector circuit for detecting the polarity of a voltage drop across said variable input resistor;

said output buffer having first and second outputs and comprising a first output buffer part connected between a power supply and said first and second outputs and a second output buffer part connected between ground and said first and second outputs;

said first output buffer part comprising a first variable current source controlled by a source bias voltage and a first group of switches configurable as conducting or non-conducting, said first variable current source and said first group of switches being series-connected between said power supply and said first and second outputs;

said second output buffer part comprising a first variable current sink controlled by a sink bias voltage and a second group of switches configurable as conducting or non-conducting, said first variable current sink and said second group of switches being series-connected between ground and said first and second outputs; and

an output control circuit connected to said first and second groups of switches which controls the state of said switches to thereby define a first switch configuration wherein said first output is connected to said current source and said second output is connected to said current sink and a second switch configuration wherein said first output is connected to said current sink and said second output is connected to said current source; and

wherein said first input is connected to said first output and said second input is connected to said second output.

24. An integrated circuit that includes a differential swing interconnect I/O buffer comprising an output buffer and an input buffer;

said input buffer having first and second inputs and comprising a first variable input resistor having resistance determined by a resistor control voltage and being connected between said first and second inputs and to an input detector circuit for detecting the polarity of a voltage drop across said variable input resistor;

said output buffer having first and second outputs and comprising a first output buffer part connected between a power supply and said first and second outputs and a second output buffer part connected between ground and said first and second outputs;

said first output buffer part comprising a first variable current source controlled by a source bias voltage and a first group of switches configurable as conducting or non-conducting, said first variable current source and said first group of switches being series-connected between said power supply and said first and second outputs;

said second output buffer part comprising a first variable current sink controlled by a sink bias voltage and a second group of switches configurable as conducting or non-conducting, said first variable current sink and said second group of switches being series-connected between ground and said first and second outputs; and

an output control circuit connected to said first and second groups of switches which controls the state of said switches to thereby define a first switch configuration wherein said first output is connected to said current source and said second output is connected to said current sink and a second switch configuration wherein said first output is connected to said current sink and said second output is connected to said current source;

said integrated circuit being connected to a reference resistor and further including a current bias reference circuit which generates said source bias voltage and said sink bias voltage, said current bias reference circuit being connected to a high input reference voltage and a low input reference voltage and comprising;

a first current bias reference circuit part connected between said power supply and said reference resistor at a first reference node and comprising a second variable current source controlled by said source bias voltage;

a second current bias reference circuit part connected between ground and said reference resistor at a second reference node and comprising a second variable current sink controlled by said sink bias voltage; and

a first feedback circuit that generates said source bias voltage with magnitude such that the voltage at said first reference node is substantially equal to said high input reference voltage and that generates said sink bias voltage with magnitude such that the voltage at said second reference node is substantially equal to said low input reference voltage, said first feedback circuit being connected so that the magnitude of the current through said second variable current source is inversely dependent on the voltage at said first reference node and the magnitude of the current through said second variable current sink is dependent on the voltage at said fourth node.

25. The circuit of claim 24 wherein said first current bias reference circuit part has substantially the same operating characteristics as said first output buffer part and said second current bias reference circuit part has substantially the same operating characteristics as said second output buffer part.

26. The circuit of claim 24, further including a resistor bias reference circuit for generating an active resistor biasing voltage and being connected to at least one of said high and low input reference voltages, wherein said resistor control voltage is equal to said active resistor biasing voltage and said resistor bias reference circuit comprises:

a first resistor bias reference circuit part connected between said power supply and a second variable input resistor at a third reference node, said second variable input resistor controlled by said active resistor biasing voltage, said first resistor bias reference circuit part comprising a third variable current source biased to said source bias voltage;

a second resistor bias reference circuit part connected between ground and said second variable input resistor at a fourth reference node, said second resistor bias reference circuit part comprising a third variable current sink controlled by said sink bias voltage; and

a second feedback circuit that generates said active resistor biasing voltage with magnitude such that the voltage at said third reference node is substantially equal to said high input reference voltage and the voltage at said fourth reference node is substantially equal to said low input reference voltage.

27. The circuit of claim 26 wherein said second variable input resistor has substantially the same operating characteristics as said first variable input resistor in said input buffer, said first resistor bias reference circuit part has substantially the same operating characteristics as said first output buffer part, and said second resistor bias reference circuit part has substantially the same operating characteristics as said second output buffer part.

28. The circuit in claim 26 wherein said first input is connected to said first output at a first I/O node and said second input is connected to said second output at a second I/O node.

29. The circuit in claim 28 wherein each of said first, second, and third variable current source comprises a MOS transistor with a gate voltage equal to said source bias voltage.

30. The circuit in claim 28 wherein each of said first, second, and third variable current sink comprises a MOS transistor with a gate voltage equal to said sink bias voltage.

31. The circuit in claim 28 wherein said first group of switches comprises a first switch connected between said first variable current source and said first I/O node and a second switch connected between said first variable current source and said second I/O node, and said second group of switches comprises a third switch connected between said first I/O node and said first variable current sink and a fourth switch connected between said second I/O node and said first variable current sink.

32. The circuit in claim 31 wherein each of said first through fourth switches comprises a MOS transistor.

33. The circuit in claim 28 wherein said first variable input resistor comprises a MOS transistor with a gate voltage equal to said resistor control voltage.

34. The circuit in claim 33 wherein said first variable input resistor comprises a plurality of series-connected MOS transistors, each having a gate voltage equal to said resistor control voltage.

35. The circuit in claim 34 further including at least one capacitor connected between a pair of series connected MOS transistors and ground.

36. The circuit in claim 28 wherein said input detector circuit comprises a comparator.

37. The circuit in claim 28 wherein said first feedback circuit comprises a first operational amplifier having as inputs said high input reference voltage and the voltage at said first reference node and having as output said source bias voltage and a second operational amplifier having as inputs said low input reference voltage and the voltage at said second reference node and having as output said sink bias voltage.

38. The circuit in claim 37 further including at least one of a first capacitor connected between the output of said first operational amplifier and said second reference node and a second capacitor connected between the output of said second operational amplifier and said first reference node.

39. The circuit in claim 28 wherein said second feedback circuit comprises an operational amplifier having as inputs said high input reference voltage and the voltage at said third reference node and having as output said active resistor biasing voltage.

40. The circuit in claim 28 wherein said first input buffer part further comprises at least one gain-limiting resistor connected in series between said first variable current source and said first variable current sink.

41. The circuit in claim 28 further including a resistor enable circuit having a resistor enable signal, said resistor enable circuit alternatively selecting in response to said resistor enable signal a resistor control voltage as one of said active resistor biasing voltage to enable said variable input resistor and a biasing voltage with magnitude sufficient to disable said variable input resistor by placing it in a high-impedance state.

42. The circuit in claim 41 further including a third switch configuration selectable by said output control circuit wherein all switches which are connected to at least one of said first and second outputs, are in the non-conducting state.

43. The circuit of claim 42 wherein said first current bias reference circuit part and said first resistor bias reference circuit part each have substantially the same operating characteristics as said first output buffer part, said second current bias reference circuit part and said second resistor bias reference circuit part each have substantially the same operating characteristics as said second output buffer part, and said second variable input resistor has substantially the same operating characteristics as said first variable input resistor.

44. A plurality of circuits as in claim 42 connected to first and second balanced transmission lines each having a first and second end, wherein each of said circuits has said first output connected to said first transmission line and said second output connected to said second transmission line, said plurality of circuits including a first circuit connected to the transmission lines at said first ends and a second circuit connected to the transmission lines at said second ends.

45. The plurality of circuits in claim 44 wherein said first variable input resistor in said first and second circuits is enabled and said first variable input resistor in all other of said plurality of circuits is disabled.

46. A current biasing circuit that generates bias voltages for a plurality of current sources and generates a controlled voltage and current at two points, said current biasing circuit comprising:

a first voltage controlled current source series connected between a supply voltage and a reference resistor at a first node;

a first voltage controlled current sink series connected between ground and said reference resistor at a second node;

a first feedback circuit having inputs connected to a first reference voltage and said first node and having an output connected to said first voltage controlled current source, whereby said first feedback circuit biases said first voltage controlled current source so that the voltage at said first node is substantially equal to said first reference voltage; and

a second feedback circuit having inputs connected to a second reference voltage and said second node and having an output connected to said first voltage controlled current sink, whereby said second feedback circuit biases said first voltage controlled current sink so that the voltage at said second node is substantially equal to said second reference voltage.

47. An active resistor control circuit biased by the current biasing circuit of claim 46, said resistor control circuit comprising:

a second voltage controlled current source series connected between said power supply and a voltage controlled resistor at a third node, said second current source sourcing a current determined by the output voltage of said first feedback circuit;

a second voltage controlled current sink series connected between ground and said voltage controlled resistor at a fourth node, said second current sink sinking a current determined by the output voltage of said second feedback circuit; and

a third feedback circuit having inputs connected to said second reference voltage and the voltage at said fourth node and having an output connected to said voltage controlled resistor, whereby said third feedback circuit biases said voltage controlled resistor so that the voltage at said fourth node is substantially equal to said second reference voltage.

48. The current biasing circuit of claim 46, further comprising at least one of a first capacitor connected between said second node and the output of said first feedback circuit and a second capacitor connected between said first node and the output of said second feedback circuit.

49. The current biasing circuit of claim 46, wherein said first and second feedback circuits comprise operational amplifiers.

50. An output buffer circuit biased by the current biasing circuit of claim 48, wherein said output buffer circuit comprises:

an output current source connected between said power supply and a current switch and sourcing a current determined by the output voltage of said first feedback circuit; and

an output current sink connected between said current switch and ground and sinking a current determined by the output voltage of said second feedback circuit;

wherein a load may be connected to said output current source and output current sink through said current switch.

51. An active resistor control circuit biased by the current biasing circuit of claim 46, said resistor control circuit comprising:

a second voltage controlled current source series connected between said power supply and a voltage controlled resistor at a third node, said second current source sourcing a current determined by the output voltage of said first feedback circuit;

a second voltage controlled current sink series connected between ground and said voltage controlled resistor at a fourth node, said second current sink sinking a current determined by the output voltage of said second feedback circuit; and

a third feedback circuit having inputs connected to said first reference voltage and the voltage at said third node and having an output connected to said voltage controlled resistor, whereby said third feedback circuit biases said voltage controlled resistor so that the voltage at said third node is substantially equal to said first reference voltage.

52. The resistor control circuit of claim 51, wherein said third feedback circuit comprises an operational amplifier.

53. An input buffer circuit biased by the resistor control circuit of claim 51, wherein said input buffer comprises a voltage controlled input resistor having a resistance determined by the output voltage of said third feedback circuit.

54. An input buffer circuit biased by the resistor control circuit of claim 47, wherein said input buffer comprises a voltage controlled input resistor having a resistance determined by the output voltage of said third feedback circuit.

55. The resistor control circuit of claim 47, wherein said third feedback circuit comprises an operational amplifier.