Low-latency small-swing clocked receiver

• US 5,977,798 A
• Filed: 07/18/1997
• Issued: 11/02/1999
• Est. Priority Date: 02/28/1997
• Status: Expired due to Term

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Zerbe, Jared L.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): LE, DON P
• Application Number:
  US08/896,934
• Time in Patent Office: 837 Days
• Field of Search: 326/82, 326/83, 326/86, 326/93, 326/95, 326/97, 326/98, 326/115, 326/121, 327/55, 327/67
• US Class Current: 326/98
• CPC Class Codes: H03K 3/356121 with synchronous operation H03K3/35613, H03K3/356147 take precedence
• CPC Class Codes: H04L 25/0276 Arrangements for coupling common mode signals
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end

Abstract

The present invention achieves the stated input receiver goals by merging many of the different functions required into a single unit instead of serializing them in the more traditional fashion. The present invention provides a receiver circuit having both a source-follower pair of MOS transistors, and a source-coupled pair of MOS transistors. The connecting node between these two pairs is coupled to a sense amplifier. The simultaneous use of the source-follower pair, the source-coupled pair and the sense-amplifier transistors allows for fast amplification of the low-swing input to full-rail CMOS, when triggered by a CMOS input clock.

Claims

1. A receiver circuit comprising:

a source follower pair of MOS transistors having a pair of sources comprising a pair of nodes, each source follower transistor having a gate coupled in a first configuration to each of a pair of differential inputs;

a source coupled pair of MOS transistors having a pair of drains coupled to said pair of nodes, each source coupled transistor having a gate coupled in a second configuration to each of a pair of differential inputs; and

a sense amplifier coupled to said nodes and receiving a clock signal, the signals at the pair of nodes being converted from small swing signals into CMOS signals within a period of the clock signal.

2. The circuit of claim 1 wherein said MOS transistors are nMOS transistors.

3. The circuit of claim 1 further comprising first and second pre-discharge transistors coupled to said nodes, and having gates coupled to a clock input.

4. The circuit of claim 1 further comprising:

a first power savings transistor connected between a first one of said source coupled transistors and a first one of said nodes, and having a gate coupled to a second one of said nodes; and

a second power savings transistor connected between a second one of said source coupled transistors and a second one of said nodes, and having a gate connected to said first one of said nodes.

5. The circuit of claim 1 wherein said source follower transistors have a Vt of approximately 300 millivolts or less.

6. The circuit of claim 1 further comprising:

first and second inverters having inputs connected to respective ones of said nodes, and outputs connected as outputs of said receiver circuit.

7. The circuit of claim 6 wherein said inverters have a trip point at a voltage level above a point of separation of said nodes during amplification by said sense amplifier.

8. The circuit of claim 7 wherein said voltage level is approximately 200 millivolts above said point of separation.

9. The circuit of claim 1 further comprising:

a power down transistor connected between a power supply and the drains of said source follower pair of MOS transistors, said power down transistor having a gate coupled to a power down line.

10. The circuit of claim 9 wherein said power down transistor has a W/L ratio of greater than 100.

11. A receiver circuit comprising:

a source follower pair of MOS transistors having a pair of sources comprising a pair of nodes, each source follower transistor having a gate coupled in a first configuration to each of a pair of differential inputs;

a source coupled pair of MOS transistors having a pair of drains coupled to said pair of nodes, each source coupled transistor having a gate coupled in a second configuration to each of a pair of differential inputs;

a sense amplifier coupled to said nodes;

first and second pre-discharge transistors coupled to said nodes, and having gates coupled to a clock input;

a first power savings transistor connected between a first one of said source coupled transistors and a first one of said nodes, and having a gate coupled to a second one of said nodes;

a second power savings transistor connected between a second one of said source coupled transistors and a second one of said nodes, and having a gate connected to said first one of said nodes;

first and second inverters having inputs connected to respective ones of said nodes, and outputs connected as outputs of said receiver circuit; and

a power down transistor connected between a power supply and the drains of said source follower pair of MOS transistors, said power down transistor having a gate coupled to a power down line.

12. The circuit of claim 11 wherein said inverters have a trip point at a voltage level above a point of separation of said nodes during amplification by said sense amplifier.

13. The circuit of claim 12 wherein said voltage level is approximately 200 millivolts above said point of separation.

14. The circuit of claim 11 wherein said source follower transistors have a Vt of approximately 300 millivolts or less.

15. The circuit of claim 11 wherein said power down transistor has a W/L ratio of greater than 100.