Differential MOS current-mode logic circuit having high gain and fast speed
First Claim
1. A differential MOS current-mode logic circuit comprising:
- a first transistor coupled to a second transistor at a common source, wherein a differential input signal is applied to the gates of the first and second transistors such that when one transistor is on, the other transistor is off;
a first complementary transistor having a gate coupled to the gate of the first transistor and having a drain coupled to a drain of the first transistor forming a first common drain node wherein a first current through the first complementary transistor is decreased when the first transistor is on and is increased when the first transistor is off so as to increase the gain and the switching speed at the first common node;
a second complementary transistor having a gate coupled to the gate of the second transistor and having a drain coupled to a drain of the first transistor forming a second common drain node wherein a second current through the second complementary transistor is decreased when the second transistor is on and is increased when the second transistor is off so as to increase the gain and the switching speed at the second common node;
a first diode and a second diode coupled to limit the voltages at the first and second common drain nodes, respectively, wherein the first and second diodes provides a current path for a bias current;
a first current source coupled to the common source of the first and second transistors to provide a bias current to the first and second transistors wherein a first output signal is generated at the first common drain node and a second output signal is generated at the second common drain node;
third and fourth transistors coupled in parallel and having a first common node coupled to said first common current source and having a second common node coupled to supply a second output signal wherein a gate of said third transistor is coupled to a third input signal and a gate of said fourth transistor is coupled to a fourth input signal; and
third and fourth complementary transistors coupled together in parallel and coupled between said second common node of said third and fourth transistors and said supply voltage wherein a gate of said third complementary transistor is coupled to said gate of said third transistor and wherein a gate of said fourth complementary transistor is coupled to said gate of said fourth transistor.
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Abstract
The differential MOS current-mode logic structure of the present invention is comprised of a differential MOS transistor pair and a complementary MOS (CMOS) transistor for each of the transistors comprising the differential MOS pair. The gates of the CMOS transistors are coupled to the gates of the differential MOS pair. Since the gates of the differential MOS pair receive a differential signal from the inputs, the voltage between the gate and the source, Vgs, for each of the transistors comprising the MOS differential pair is not fixed. As a result, the gain of the CMOS current-mode logic structure of the present invention is high. In addition, since the gates of the CMOS transistors are coupled to the gates of the differential MOS pair, the current for the CMOS transistors is increased when charging the node capacitance and is decreased when discharging the node capacitance. Hence, the present invention allows faster charging and discharging of transistors, which results in faster switching transistors and higher speed circuit.
30 Citations
19 Claims
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1. A differential MOS current-mode logic circuit comprising:
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a first transistor coupled to a second transistor at a common source, wherein a differential input signal is applied to the gates of the first and second transistors such that when one transistor is on, the other transistor is off; a first complementary transistor having a gate coupled to the gate of the first transistor and having a drain coupled to a drain of the first transistor forming a first common drain node wherein a first current through the first complementary transistor is decreased when the first transistor is on and is increased when the first transistor is off so as to increase the gain and the switching speed at the first common node; a second complementary transistor having a gate coupled to the gate of the second transistor and having a drain coupled to a drain of the first transistor forming a second common drain node wherein a second current through the second complementary transistor is decreased when the second transistor is on and is increased when the second transistor is off so as to increase the gain and the switching speed at the second common node; a first diode and a second diode coupled to limit the voltages at the first and second common drain nodes, respectively, wherein the first and second diodes provides a current path for a bias current; a first current source coupled to the common source of the first and second transistors to provide a bias current to the first and second transistors wherein a first output signal is generated at the first common drain node and a second output signal is generated at the second common drain node; third and fourth transistors coupled in parallel and having a first common node coupled to said first common current source and having a second common node coupled to supply a second output signal wherein a gate of said third transistor is coupled to a third input signal and a gate of said fourth transistor is coupled to a fourth input signal; and third and fourth complementary transistors coupled together in parallel and coupled between said second common node of said third and fourth transistors and said supply voltage wherein a gate of said third complementary transistor is coupled to said gate of said third transistor and wherein a gate of said fourth complementary transistor is coupled to said gate of said fourth transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A differential MOS current-mode logic circuit comprising:
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first and second transistors coupled in series wherein said second transistor is coupled to a first common current source which is coupled to ground wherein a gate of said first transistor is coupled to a first input signal and a gate of said second transistor is coupled to a second input signal; first and second complementary transistors coupled together in series and coupled between said first and second transistors and a supply voltage wherein a gate of said first complementary transistor is coupled to said gate of said first transistor and wherein a gate of said second complementary transistor is coupled to said gate of said second transistor and wherein a first output signal is taken between said second complementary transistor and said first transistor; third and fourth transistors coupled in parallel and having a first common node coupled to said first common current source and having a second common node coupled to supply a second output signal wherein a gate of said third transistor is coupled to a third input signal and a gate of said fourth transistor is coupled to a fourth input signal; and third and fourth complementary transistors coupled together in parallel and coupled between said second common node of said third and fourth transistors and said supply voltage wherein a gate of said third complementary transistor is coupled to said gate of said third transistor and wherein a gate of said fourth complementary transistor is coupled to said gate of said fourth transistor. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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Specification