Frequency synthesis circuit tuned by digital words

• US 5,977,805 A
• Filed: 01/21/1998
• Issued: 11/02/1999
• Est. Priority Date: 01/21/1998
• Status: Expired due to Term

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Valenti, Didier, Vergnes, Alain
• Primary Examiner(s): Wells, Kenneth B.
• Assistant Examiner(s): NGUYEN, MINH T
• Application Number:
  US09/010,434
• Time in Patent Office: 650 Days
• Field of Search: 327/105, 327/107, 327/241, 327/269, 327/276, 327/284, 327/277, 327/156, 327/147, 327/407, 327/270, 327/271, 327/149, 327/152, 327/161, 331/34, 375/327, 375/373-376
• US Class Current: 327/107
• CPC Class Codes: H03B 28/00 Generation of oscillations by methods not covered by groups H03B5/00 - H03B27/00, including modification of the waveform to produce sinusoidal oscillations analogue function generators for performing computing operations G06G7/26; use of transformers for conversion of waveform in ac-ac converters H02M5/18
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/16 Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop

Abstract

A direct digital frequency synthesizer featuring an accumulator having a modulo overflow signal addressing a multiplexer. The multiplexer receives a series of delay signals generated from digital circuits. The delay signals establish the phase of a reference oscillator. The number of units of delay are sufficient to resolve expected jitter. The accumulator is a digital counter which increments by only a single digit for each count, such as a Gray code counter. In one embodiment, the delay signals are generated by a charge pump feeding individual logic circuits driving integrated capacitors in a loop. Feedback to the charge pump establishes that the total delay will subdivide a single clock cycle of the reference clock. In a second embodiment, a single shifter or several shifters, with output in phase reversal relation, subdivide a single clock cycle. A clock multiplier and divider are used to assure the synchronism of each clock cycle with the total number of units of delay. The output of the multiplexer is the reference oscillator signal, adjusted by the phase delay, forming a synthesized output frequency.

Claims

1. A frequency synthesis circuit whose output frequency is determined by input digital words comprising,

an input line receiving the input digital words for tuning the output frequency of the frequency synthesis circuit,

a local oscillator producing a local oscillator signal having a local oscillator frequency,

a delay line connected to the local oscillator having a plurality of selectable delays corresponding to a plurality of incremental phase shifts relative to the local oscillator signal, spanning one cycle of the local oscillator frequency,

a multiplexer connected to receive the plurality of selectable delays from the delay line to produce an output signal corresponding to the local oscillator frequency with a selected phase delay as indicated by a digital word,

a modulo accumulator connected to the input line to receive the input digital words determinative of desired output frequency and to transmit corresponding accumulator overflow signals to a second accumulator producing second digital words transmitted to the multiplexer, whereby the multiplexer selects a delay corresponding to the accumulator overflow signals which depends on the input digital words,

whereby the local oscillator frequency, repeatedly shifted by unit phase delay corresponding to said input digital words, forms a synthesized output waveform whose output frequency depends on the input digital words.

2. The circuit of claim 1 having an input word shaping circuit including the modulo accumulator with an input connected to receive the input digital wards from a transmission path, the input word shaping circuit converting the transmitted digital words to shaped digital words.

3. The circuit of claim 1 wherein the second accumulator is a digital counter which increments by only a single digit for each count.

4. The circuit of claim 3 wherein the digital counter is a Gray code counter.

5. The circuit of claim 2 wherein the input word shaping circuit comprises an integrator in series with a threshold level detection circuit, said integrator being said modulo accumulator.

6. The circuit of claim 1 wherein the delay line comprises a plurality of buffer circuits in series, the buffer circuits connected to a charge pump loading a filter which loads each buffer of the series of buffer circuits with an increasing incremental charge, providing a phase delay to the output frequency of the local oscillator.

7. The circuit of claim 2 wherein the input word shaping circuit is connected to the multiplexer output signal for clocking.

8. The circuit of claim 1 wherein a phase lock loop is connected to said delay line in a manner to regulate the incremental delays to span one cycle of the established clock frequency.

9. The circuit of claim 1 wherein the delay line comprises a plurality of serially connected capacitively loaded circuits and a charge pump, each successive loaded circuit having an increasing amount of capacitive delay in individual unit of delay as adjusted by the charge pump.

10. The circuit of claim 1 wherein the delay line comprises at least one shifter, the shifter having a plurality of outputs dividing a clock cycle of the local oscillator into units of delay delivered to said multiplexer.

11. The circuit of claim 10 wherein the first and second shifters each comprise a plurality of D flip-flops connected in series clocked by the local oscillator signal from the local oscillator at a frequency multiplied by an integer.

12. The circuit of claim 11 wherein the local oscillator signal is supplied to the second shifter in phase reversal relation relative to the local oscillator signal supplied to the first shifter.

13. A frequency synthesis circuit whose output frequency is determined by input digital words comprising,

an input line receiving the input digital words, each word being K bits wide and establishing control of the phase of a local oscillator,

a modulo-2^L accumulator connected to the input line to receive the input digital words therefrom, where L is the size in bits of said accumulator, and whose output is connected to a threshold circuit wherein the threshold circuit establishes an absolute threshold value of the accumulator and provides an accumulator overflow signals whenever the output of the accumulator exceeds the absolute threshold value, the accumulator also having a clock terminal,

a delay line connected to the local oscillator having a plurality of selectable delays corresponding to a plurality of incremental phase shifts relative to the output frequency of the local oscillator, spanning one cycle of the local oscillator frequency,

a multiplexer connected to receive the plurality of selectable delays from the delay line and to the output of the threshold circuit to produce an output signal corresponding to the local oscillator frequency with a selected phase delay as incremented by the accumulator overflow signal, the output of the multiplexer fed back to the clock terminal of the accumulator,

whereby the local oscillator frequency, repeatedly shifted by selected amounts of delay corresponding to the input digital words, forms a synthesized output waveform whose frequency depends on said input digital words.

14. The circuit of claim 13 wherein the delay line comprises a plurality of buffer circuits in series, the buffer circuits connected to a charge pump which loads each buffer of the series of buffer circuits with an increasing incremental delay, providing a phase delay to the output frequency of the local oscillator.

15. The circuit of claim 13 wherein the multiplexer is connected to the output of the threshold circuit through a digital counter that receives the accumulator overflow signal from the threshold circuit and which increments by only a single digit for each occurrence of the accumulator overflow signal, the digital counter providing a phase delay selection value to a control input o f the multiplexer.

16. The circuit of claim 13 wherein a phase lock loop is connected to said delay line in a manner to regulate the incremental delays to span one cycle of the established clock frequency.

17. The circuit of claim 13 wherein the delay line comprises a plurality of serially connected capacitively loaded circuits and a charge pump associated with a filter, each successive circuit having an increasing amount of delay in individual units of delay as adjusted by the charge pump.

18. The circuit of claim 13 wherein the local oscillator signal is supplied to the second shifter in phase reversal relation relative to the local oscillator signal supplied to the first shifter, each shifter having a plurality of outputs dividing a clock cycle of the local oscillator into units of delay delivered to said multiplexer.

19. The circuit of claim 18 wherein the first and second shifters each comprises a plurality of D flip-flops clocked by the local oscillator at a frequency multiplied by an integer.

20. The circuit of claim 18 wherein the local oscillator signal is supplied to the second shifter in phase reversal relation relative to the local oscillator signal supplied to the first shifter.

21. A frequency synthesis circuit whose output frequency is determined by input digital words, comprising:

an input line receiving said input digital words determinative of the output frequency;

a modulo accumulator coupled to the input line for integrating the values of the input digital words, the accumulator providing successive phase selection values on an output thereof;

a local oscillator producing an oscillator signal having a reference frequency;

a delay line connected to the local oscillator to receive the oscillator signal therefrom, the delay line producing a plurality of versions of the oscillator signal with different delays, the delays corresponding to a plurality of incremental phase shifts of the received oscillator signal at the reference frequency, the plurality of incremental phase shifts spanning one cycle of the oscillator signal at the reference frequency; and

a multiplexer connected to the delay line to receive the plurality of phase shifted versions of the oscillator signal therefrom, the multiplexer having a control input connected to the output of the accumulator to receive successive phase selection values therefrom, the multiplexer repeatedly selecting one of said plurality of phase shifted versions of the oscillator signal as an output of the circuit in accord with the successive phase selection values, whereby the repeatedly phase shifted selections form a synthesized output frequency.

22. The circuit of claim 21 wherein the accumulator is coupled indirectly to the input line via an input word shaping circuit connected therebetween, the input word shaping circuit comprising an integrator in series with a threshold level detection circuit, the input word shaping circuit converting the received input digital words to successive pulses having a period defined by said input digital words, the accumulator comprising a digital counter incremented by each successive pulse.

23. The circuit of claim 22 wherein said digital counter is a Gray code counter.

24. The circuit of claim 22 wherein said integrator and accumulator are clocked by the output of the multiplexer.

25. The circuit of claim 21 wherein the delay line comprises a plurality of buffer circuits in series, the buffer circuits connected to a charge pump which loads each buffer of the series of buffer circuits with an increasing incremental delay, providing a phase delay to the output frequency of the local oscillator.

26. The circuit of claim 21 wherein a phase lock loop is connected to said delay line in a manner to regulate the incremental delays to span one cycle of the local oscillator frequency.

27. The circuit of claim 21 wherein the delay line comprises a plurality of serially connected capacitively loaded circuits and a charge pump associated with a filter, each successive circuit having an increasing amount of delay in individual unit of delay as adjusted by the charge pump.

28. The circuit of claim 21 wherein the delay line comprises at least one shifter, the shifter having a plurality of outputs dividing a clock cycle of the local oscillator into units of delay delivered to said multiplexer.

29. The circuit of claim 28 wherein a phase lock loop is connected to said delay line in a manner to regulate the incremental delays to span one cycle of the local oscillator frequency.

30. The circuit of claim 29 wherein the first and second shifters each comprise a plurality of D flip-flops clocked by the local oscillator signal at a frequency multiplied by an integer.

31. The circuit of claim 29 wherein the delay line comprises a plurality of serially connected capacitively loaded circuits and a charge pump, each successive loaded circuit having an increasing amount of capacitive delay in individual unit of delay as adjusted by the charge pump.