Low noise transistor module and amplifier
First Claim
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1. A low noise transistor integrated circuit module having an effective gate width Weff comprisinga cell including k FETs each having a gate length L and a gate width W=Weff N, where k=1, 2 . . . said FETs being electrically connected in parallel with one another when k>
- 1, and each of said FETs having a gate width of about 2.5 μ
m or less,a plurality m of said cells being topologically arranged in a row and being electrically connected in parallel with one another, anda plurality n of said rows being arranged topologically parallel to one another and being electrically connected in parallel with one another, so that said effective gate width of said module is increased by a factor of kmn=N compared to said gate width W, thereby to decrease the gate resistance and noise figure of said module compared to a single transistor having a gate width Weff.
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Abstract
A low noise transistor IC or module comprises a plurality of conventional CMOS transistors which are laid out in parallel in such a way that the effective gate width of the combination of transistors is increased, yet the effective gate resistance and hence the noise figure (NF) of the circuit are reduced. A low noise amplifier incorporating such a module is also described.
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Citations
8 Claims
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1. A low noise transistor integrated circuit module having an effective gate width Weff comprising
a cell including k FETs each having a gate length L and a gate width W=Weff N, where k=1, 2 . . . said FETs being electrically connected in parallel with one another when k> - 1, and each of said FETs having a gate width of about 2.5 μ
m or less,a plurality m of said cells being topologically arranged in a row and being electrically connected in parallel with one another, and a plurality n of said rows being arranged topologically parallel to one another and being electrically connected in parallel with one another, so that said effective gate width of said module is increased by a factor of kmn=N compared to said gate width W, thereby to decrease the gate resistance and noise figure of said module compared to a single transistor having a gate width Weff. - View Dependent Claims (2, 3, 4)
- 1, and each of said FETs having a gate width of about 2.5 μ
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5. A low noise amplifier comprising
a transistor circuit for providing gain, and a current source coupled to said gain circuit, said current source comprising a first transistor circuit for providing a load to said gain circuit and a second transistor circuit for biasing said first circuit, characterized in that said first and second circuits each comprise a low noise transistor integrated circuit module having an effective gate width Weff each of said modules including a cell including k FETs each having a gate length L and a gate width W=Weff /N, where k=1, 2 . . . said FETs being electrically connected in parallel with one another when k> - 1,
a plurality m of said cells being topologically arranged in a row and being electrically connected in parallel with one another, and a plurality n of said rows being arranged topologically parallel to one another and being electrically connected in parallel with one another, so that said effective gate width of said module is increased by a factor of kmn=N compared to said gate width W, thereby to decrease the gate resistance and noise figure of said module compared to a single transistor having a gate width Weff.
- 1,
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6. A method of reducing the noise figure of an amplifier comprising fabricating a low noise transistor module having an effective gate width Weff by the steps of
forming a cell including k FETs each having a gate length L and a gate width W=Weff /N, where k=1, 2 . . . said FETs are electrically connected in parallel with one another when k> - 1, and each of said FETs has a gate width of about 2.5 μ
m or less,laying out a plurality m of the cells so that topologically they are arranged in a row and electrically they are connected in parallel, laying out a plurality n of said rows so that they are topologically arranged parallel to one another and electrically they are connected in parallel with one another, so that said effective gate width of said module is increased by a factor kmn=N compared to the gate width W, thereby to decrease the gate resistance of the module and the noise figure of the amplifier compared to a single transistor having a gate width Weff. - View Dependent Claims (7, 8)
- 1, and each of said FETs has a gate width of about 2.5 μ
Specification
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Current AssigneeAvago Technologies General IP PTE Limited (Broadcom, Inc.)
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Original AssigneeLucent Technologies, Inc. (Nokia Corporation)
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InventorsGeorgiou, George E., Chen, Young-Kai
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Primary Examiner(s)Pascal, Robert
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Assistant Examiner(s)Nguyen, Patricia T.
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Application NumberUS08/974,816Time in Patent Office712 DaysField of Search330/277, 330/308, 257/202, 257/207, 257/401, 257/204, 257/208US Class Current330/277CPC Class CodesH01L 27/0207 Geometrical layout of the c...H03F 1/26 Modifications of amplifiers...H03F 2200/294 the amplifier being a low n...H03F 2200/372 Noise reduction and elimina...
