Data resampler for data processing system for logically adjacent data samples
First Claim
1. A data resampler for a data processing system processing logically adjacent data samples, said data sampler comprising:
- a memory subsystem, for storing at least a first plurality of data samples to be rendered;
a digital differential analyzer (DDA), responsive to DDA parameter sets, for generating an interpolation corner address for said plurality of data samples to be rendered, and for also generating a set of interpolation fractions;
a fetch unit, for receiving the generated interpolation corner address and for generating four source addresses of data samples to be fetched from said memory subsystem;
a first FIFO memory, for holding said interpolation fractions and for permitting said DDA and fetch unit to continue to operate during memory read latency periods;
a second FIFO memory, for holding pixel data;
a first address generator;
an address cache and a data cache, wherein said data cache comprises at least two cache lines each holding two memory words and wherein said address cache comprises at least two cache lines each comprised of two address registers, each address register for holding an address of a word in said memory subsystem; and
an interpolation unit, for receiving pixel data from said second FIFO memory and interpolation fractions from said first FIFO memory, for computing rendered result pixels, for assembling said result pixels into memory words, and for outputting said memory words to a destination memory address supplied by said address generator in a destination memory subsystem via a third FIFO.
9 Assignments
0 Petitions
Accused Products
Abstract
A data resampler for a data processing system for logically adjacent data samples is provided. The data resampler includes a memory subsystem for storing samples to be rendered, a digital differential analyzer (DDA) for generating an interpolation corner address for a sample to be rendered and which also generates a set of interpolation fractions. The resampler also includes a fetch unit, which receives the generated interpolation corner address and generates four source addresses of samples to be fetched from the memory subsystem. A number of memory units are included in the resampler. The first memory unit is a first in, first out FIFO memory, for holding the generated interpolation fractions and for permitting the DDA and fetch unit to continue to operate during memory read latency periods. The second memory unit is also a FIFO memory and is used to hold pixel data. The resampler further includes an interpolation unit, which receives pixel data from the second FIFO memory unit and interpolation fractions from the first FIFO memory unit. The interpolation unit then computes rendered result pixels, assembles the result pixels into memory words and outputs the words to a destination memory address, which is supplied by an address generator in a destination memory subsystem via a third FIFO memory unit.
-
Citations
24 Claims
-
1. A data resampler for a data processing system processing logically adjacent data samples, said data sampler comprising:
-
a memory subsystem, for storing at least a first plurality of data samples to be rendered; a digital differential analyzer (DDA), responsive to DDA parameter sets, for generating an interpolation corner address for said plurality of data samples to be rendered, and for also generating a set of interpolation fractions; a fetch unit, for receiving the generated interpolation corner address and for generating four source addresses of data samples to be fetched from said memory subsystem; a first FIFO memory, for holding said interpolation fractions and for permitting said DDA and fetch unit to continue to operate during memory read latency periods; a second FIFO memory, for holding pixel data; a first address generator; an address cache and a data cache, wherein said data cache comprises at least two cache lines each holding two memory words and wherein said address cache comprises at least two cache lines each comprised of two address registers, each address register for holding an address of a word in said memory subsystem; and an interpolation unit, for receiving pixel data from said second FIFO memory and interpolation fractions from said first FIFO memory, for computing rendered result pixels, for assembling said result pixels into memory words, and for outputting said memory words to a destination memory address supplied by said address generator in a destination memory subsystem via a third FIFO. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
-
12. A method of resampling data for a data processing system for logically adjacent data samples, said method comprising:
-
storing at least data samples to be rendered in a memory subsystem; generating, in response to digital differential analyzer (DDA) parameter sets stored in DDA parameter set registers, an interpolation corner address for a sample to be rendered and a set of interpolation fractions using a digital differential analyzer (DDA); receiving the generated interpolation corner address and responsive to said received interpolation corner address, generating four source addresses of samples to be fetched from said memory subsystem using an address cache; comparing said four source addresses with all addresses resident in four working address registers of said address cache; determining if any new address needs to be fetched from said memory subsystem and fetching any required address from said memory subsystem; holding said interpolation fractions in a FIFO memory to permit said DDA to continue to operate during memory read latency periods; holding pixel data in a second FIFO; and receiving pixel data from said second FIFO and interpolation fractions from said first FIFO and computing rendered result pixels, assembling said result pixels into memory words, outputting said words to a destination memory address supplied by an address generator in a destination memory subsystem via a third FIFO, and reloading DDA parameter set registers after each DDA rendering cycle. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
-
Specification