Method of anti-fuse repair

• US 5,978,248 A
• Filed: 02/25/1998
• Issued: 11/02/1999
• Est. Priority Date: 08/20/1996
• Status: Expired due to Term

• Current Assignee: Conversant Intellectual Property Management Inc (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Micron Technology, Inc.
• Inventors: Marr, Kenneth W., Batra, Shubneesh
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US09/030,130
• Time in Patent Office: 615 Days
• Field of Search: 365/96, 365/225.7, 365/100, 365/103, 257/530
• US Class Current: 365/96
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit anti-fuse is described which is fabricated as a capacitor using a layer of oxide. The two plates of the anti-fuse are coupled to appropriate voltage levels to rupture the oxide and form a conductive short between the plates. One of the plates is formed as a diffused well which is coupled to an external voltage during programming. The well is biased to an internal voltage during normal operation of the circuit incorporating the anti-fuse.

Claims

1. An integrated circuit comprising:

an anti-fuse having an insulative member between first and second conductive members;

means, including logic circuitry, for selectively coupling the first conductive member to a programming voltage;

bias means, including a transistor or a resistor, coupled between the second conductive member and a ground-reference node; and

an external input connected to the second conductive member for applying an external voltage to the second conductive member during programming of the anti-fuse.

2. The integrated circuit of claim 1 wherein the programming voltage and the external voltage differ by an amount sufficient to rupture the insulative member.

3. The integrated circuit of claim 1 wherein the second conductive member includes a well in a semiconductive substrate.

4. A volatile or nonvolatile memory device comprising:

an anti-fuse having an insulative member between first and second conductive members;

means, including logic circuitry, for selectively coupling the first conductive member to a programming voltage;

an external input connected to the second conductive member for applying an external voltage to the second conductive member during programming of the anti-fuse; and

bias means, including a transistor or a resistor, coupled between the second conductive member and a reference-voltage node for providing a reference voltage to the second conductive member after programming of the anti-fuse.

5. The memory device of claim 4 wherein the first conductive member includes a polysilicon member, and the second conductive member includes a well in a semiconductive substrate.

6. A memory device comprising:

an anti-fuse having an insulative member between first and second conductive members;

means for selectively coupling the first conductive member to a programming voltage;

an external input connected to the second conductive member for applying an external voltage to the second conductive member during programming of the anti-fuse; and

bias means coupled between the second conductive member and a reference-voltage node for providing a bias voltage to the second conductive member after programming of the anti-fuse.

7. A method of operating an integrated circuit anti-fuse which includes an insulative layer between a polysilicon member and a well in a semiconductive substrate, the method comprising:

coupling the well to a first voltage;

using programming logic to couple a second voltage to the polysilicon member, with the first and second voltages being sufficiently different to rupture the insulative layer; and

using a bias circuit to couple a third voltage to the well after using the programming logic to couple the second voltage to the polysilicon member.

8. The method of claim 7 wherein the first and second voltages differ by an amount sufficient to rupture the insulative layer and the third voltage is a ground-reference voltage.

9. A method for operating an anti-fuse circuit comprising:

programming the anti-fuse circuit, the programming comprising;

coupling a first conductive plate of the anti-fuse circuit to a first programming voltage through a contact;

coupling a second conductive plate of the anti-fuse circuit to a second programming voltage from a programming logic circuit to create a current path through a gate oxide layer between the first and second conductive plates; and

operating the anti-fuse circuit by coupling the first conductive plate to a reference voltage through a bias network.

10. The method of claim 9 wherein:

coupling a first conductive plate comprises coupling a first conductive plate of the anti-fuse circuit to a first programming voltage through an external contact; and

operating the anti-fuse circuit comprises operating the anti-fuse circuit by coupling the first conductive plate to a ground voltage through a transistor or a transistor and a resistor in a bias network.

11. A method for operating a memory device comprising:

programming an anti-fuse circuit in a bank of anti-fuse circuits comprising;

identifying one of the anti-fuse circuits to be programmed;

identifying others of the anti-fuse circuits not to be programmed;

coupling a first conductive plate of each of the anti-fuse circuits to a first programming voltage through a contact;

coupling a second conductive plate of the anti-fuse circuits not to be programmed to a second programming voltage from a programming logic circuit to preserve a gate oxide layer between the first and second conductive plates; and

coupling a second conductive plate of the anti-fuse circuit to be programmed to a third programming voltage from the programming logic circuit to create a current path through a gate oxide layer between the first and second conductive plates of the anti-fuse circuit to be programmed; and

operating the anti-fuse circuits in the bank of anti-fuse circuits by coupling the first conductive plate of each of the anti-fuse circuits to a reference voltage through a bias network.

12. The method of claim 11 wherein:

coupling a first conductive plate comprises coupling a first conductive plate of each of the anti-fuse circuits to a first programming voltage through an external contact; and

operating the anti-fuse circuits comprises operating the anti-fuse circuits in the bank of anti-fuse circuits by coupling the first conductive plate of each of the anti-fuse circuits to a ground voltage through a transistor or a transistor and a resistor in a bias network.

13. The method of claim 11, further comprising:

reading the anti-fuse circuits with a power-up circuit;

latching a state of each of the anti-fuse circuits in a latch circuit after the anti-fuse circuits are read;

receiving an address in an address decoder circuit from address inputs;

comparing the address with the latched states in a compare circuit in the address decoder; and

accessing a memory cell in an array of memory cells corresponding to the address.

14. A method for operating an anti-fuse circuit comprising:

programming the anti-fuse circuit, the programming comprising;

a step for coupling a first conductive plate of the anti-fuse circuit to a first programming voltage through a contact;

a step for coupling a second conductive plate of the anti-fuse circuit to a second programming voltage from a programming logic circuit to create a current path through a gate oxide layer between the first and second conductive plates; and

a step for coupling the first conductive plate to a reference voltage through a bias network.

15. A memory device comprising:

an array of memory cells;

an address decoder coupled to the array and coupled to address inputs to decode addresses provided on the address inputs to access memory cells in the array corresponding to the addresses, the address decoder comprising;

a bank of anti-fuse circuits, each anti-fuse circuit comprising a layer of gate oxide between a first conductive plate and a second conductive plate;

a contact coupled to the first conductive plate of each of the anti-fuse circuits to couple a first programming voltage to the first conductive plates;

a programming logic circuit coupled to the second conductive plates of each of the anti-fuse circuits to couple the second conductive plate of anti-fuse circuits not to be programmed to a second programming voltage to preserve the gate oxide in the anti-fuse circuits not to be programmed and to couple the second conductive plate of an anti-fuse circuit to be programmed to a third programming voltage to create a current path through the gate oxide between the first and second conductive plates of the anti-fuse circuit to be programmed; and

a bias network coupled between a reference voltage and the first conductive plates of the anti-fuse circuits.

16. The memory device of claim 15 wherein:

the contact comprises a contact external to the memory device; and

the bias network comprises a transistor or a transistor and a resistor coupled between the first conductive plates and a ground voltage.

17. The memory device of claim 15, further comprising:

a power-up circuit coupled to each of the anti-fuse circuits to read the anti-fuse circuits;

a latch circuit in the address decoder to latch a state of each anti-fuse circuit being read; and

a compare circuit in the address decoder and coupled to the latch circuit to compare the addresses provided on the address inputs with the latched states.