Method of time multiplexing a programmable logic device

• US 5,978,260 A
• Filed: 07/20/1998
• Issued: 11/02/1999
• Est. Priority Date: 08/18/1995
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Wong, Jennifer, Trimberger, Stephen M., Carberry, Richard A., Johnson, Robert Anders
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US09/119,534
• Time in Patent Office: 470 Days
• Field of Search: 365/182, 365/189.01, 365/230.01
• US Class Current: 365/182
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H03K 19/17752 for hot reconfiguration
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration
• CPC Class Codes: H03K 19/1776 for memories

Abstract

A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration. The new configuration data may include off-chip or on-chip data. The present invention typically allocates at least one slice to user data memory and includes means for disabling access to at least one of the N memory cells.

Claims

1. A programmable logic device that is programmable in a plurality of configurations, the programmable logic device comprising:

a plurality of micro-registers, each micro-register being configured to simultaneously store a plurality of intermediate state values associated with different configurations of the programmable logic device;

a plurality of output selectors, each of the output selectors being configured to receive the intermediate state values from a corresponding micro-register; and

a plurality of storage elements, each of the storage elements being configured to provide read select signals to a corresponding output selector, wherein the read select signals are selectable independent of the configuration of the programmable logic device,

whereby the intermediate state values stored in a micro-register can be used in any of the configurations.

2. A programmable logic device that is programmable in a plurality of configurations, the programmable logic device comprising:

a plurality of micro-registers, each micro-register being configured to simultaneously store a plurality of intermediate state values associated with different configurations of the programmable logic device; and

a memory controller configured to provide write select signals to the micro-registers, wherein intermediate state values associated with a current configuration are loaded into the micro-registers in response to the write select signals, the memory controller being configured to provide the write select signals prior to each change of configuration.

3. A programmable logic device that is programmable in a plurality of configurations, the programmable logic device comprising:

a plurality of micro-registers, each micro-register being configured to simultaneously store a plurality of intermediate logic states associated with different configurations of the programmable logic device;

a plurality of output selectors, each of the output selectors being configured to selectively route intermediate logic states from a corresponding micro-register; and

a plurality of pipeline latches, each of the pipeline latches being configured to store intermediate logic states routed by a corresponding output selector.

4. A programmable logic device comprising:

a configurable logic block having a sequential logic element;

an interconnect structure for interconnecting said configurable logic block;

a plurality of programmable logic elements for configuring said configurable logic block and said interconnect structure;

a storage device configured to simultaneously store a plurality of intermediate logic states associated with different configurations of said configurable logic block;

a latch coupled to an input terminal of the storage device; and

a selector element having input terminals coupled to the sequential logic element and the storage device, and an output terminal coupled to the latch.

5. A programmable logic device comprising:

a configurable logic block;

an interconnect structure for interconnecting said configurable logic block;

a plurality of programmable logic elements for configuring said configurable logic block and said interconnect structure;

a storage device for storing a plurality of intermediate logic states of said configurable logic block;

a latch coupled to an input terminal of the storage device; and

a multiplexer which is programmable to couple an output terminal of the storage device to an input terminal of the latch, thereby re-circulating contents of the storage device.

6. The programmable logic device of claim 5, wherein the multiplexer is programmable to isolate the output terminal of the storage device from the input terminal of the latch, thereby preventing re-circulating contents of the storage device during a static mode.

7. The programmable logic device of claim 5, wherein the multiplexer is further programmable to couple an input terminal or an output terminal of the sequential logic element to the input terminal of the latch.

8. The programmable logic device of claim 5, further including a sequential logic element, wherein the multiplexer is further programmable to couple an initial value of the sequential logic element to the input terminal of the latch.

9. A programmable logic device comprising:

a configurable logic block;

an interconnect structure for interconnecting said configurable logic block;

a plurality of programmable logic elements for configuring said configurable logic block and said interconnect structure; and

a storage device configured to simultaneously store a plurality of intermediate logic states associated with different configurations of said configurable logic block, wherein the storage device is located in the interconnect structure.

10. A programmable logic device comprising:

a configurable logic block;

an interconnect structure for interconnecting said configurable logic block;

a plurality of programmable logic elements for configuring said configurable logic block and said interconnect structure; and

a storage device configured to simultaneously store a plurality of intermediate logic states associated with different configurations of said configurable logic block, wherein the storage device is located in a location independent of the configurable logic block.

11. A method of operating a programmable logic device comprising a plurality of programmable logic elements for configuring said programmable logic device, the method comprising the steps of:

providing a plurality of sets of N memory cells, wherein each set of N memory cells is associated with one of said programmable logic elements, and wherein the sets of memory cells form N memory slices, each of the N memory slices including one memory cell from each set of N memory cells;

storing configuration data in at least one of the N memory slices prior to configuring the programmable logic device;

configuring the programmable logic device in response to the configuration data; and

then

storing user data in all of the N memory slices.

12. A method of operating a programmable logic device comprising a plurality of programmable logic elements for configuring said programmable logic device, the method comprising the steps of:

providing a plurality of sets of N memory cells, wherein each set of N memory cells is associated with one of said programmable logic elements, and wherein the sets of memory cells form N memory slices, each of the N memory slices including one memory cell from each set of N memory cells; and

storing configuration data and user data in the N memory slices, wherein each memory slice contains only configuration data or only user data.

13. A programmable logic device comprising:

a plurality of programming points for controlling the configuration of the programmable logic device;

a plurality of memory bit sets, wherein each memory bit set is coupled to a corresponding one of the programming points, each memory bit set having a plurality of configuration memory cells; and

a select circuit coupled between each memory bit set and corresponding programming point, wherein each select circuit is controlled to couple one of the configuration memory cells to a programming point, and wherein the configuration memory cells in at least one of the memory bit sets store the same configuration data value, thereby configuring the associated programming point in a static mode.

14. A programmable logic device comprising:

a plurality of programmable logic elements for configuring said programmable logic device;

a plurality of sets of N memory cells, wherein each set of N memory cells is associated with one of said programmable logic elements, and wherein the sets of memory cells form N memory slices, each of the N memory slices including one memory cell from each set of N memory cells; and

means for burst accessing the N memory slices.

15. The programmable logic device of claim 14, wherein the means for burst accessing perform a burst read access of the memory slices.

16. The programmable logic device of claim 14, wherein the means for burst accessing perform a burst write access of the memory slices.

17. A programmable logic device comprising:

a first sequencer for managing a sequence of configurations of a first part of the programmable logic device; and

a second sequencer for managing a sequence of configurations of a second part of the programmable logic device.

18. The programmable logic device of claim 17, wherein the first and second sequencers operate in lock step.

19. The programmable logic device of claim 17, wherein the first and second sequencers operate independently.

20. A method of configuring a programmable logic device from a configuration memory comprising the steps of:

configuring the programmable logic device in a first configuration using a first set of configuration data stored in a slice of the configuration memory;

detecting an interrupt signal while the programmable logic device is configured in the first configuration; and

configuring the programmable logic device in a second configuration using a second set of configuration data stored in a slice of the configuration memory, wherein the programmable logic is configured in the second configuration in response to the interrupt signal.

21. The method of claim 20, wherein the interrupt signal is generated by the programmable logic device.

22. The method of claim 20, wherein the interrupt signal is generated external to the programmable logic device.

23. The method of claim 20, wherein the interrupt signal is generated a pre-determined number of cycles after the programmable logic device is configured in the first configuration.

24. A method of operating a programmable logic device comprising the steps of:

configuring the programmable logic device in a first configuration;

generating one or more internal signals with the programmable logic device in the first configuration;

and then configuring the programmable logic device in a second configuration or a third configuration, wherein the second or third configuration is selected in response to the one or more internal signals.

25. A method of operating a programmable logic device comprising the steps of:

providing a plurality of memory slices on the programmable logic device, wherein each of the memory slices is programmable to store a set of configuration data values for configuring said programmable logic device; and

sequentially accessing only a subset of the memory slices to configure said programmable logic device.

26. A method of operating a programmable logic device comprising the steps of:

providing a plurality N of memory slices, wherein each of the memory slices is programmable to store a set of configuration data values for configuring said programmable logic device;

providing a plurality M of storage devices for storing a plurality of intermediate states of the programmable logic device, wherein M is greater than N;

sequentially configuring the programmable logic device in a number of configurations greater than N and less than or equal to M, wherein intermediate states associated with the configurations are stored in the storage devices.

27. The method of claim 26, further comprising the steps of:

loading X of the memory slices with configuration data, wherein X is less than or equal to N;

configuring the programmable logic device in X configurations in response to the configuration data stored by the X memory slices;

storing X sets of intermediate states associated with the X configurations in the storage devices;

loading Y of the memory slices with configuration data, wherein X is less than or equal to N, and wherein X plus Y is greater than N and less than or equal to M;

configuring the programmable logic device in Y configurations in response to the configuration data stored by the Y memory slices; and

storing Y sets of intermediate states associated with the Y configurations in the storage device, wherein the X and Y sets of intermediate states are simultaneously stored in the storage device.

28. A method of operating a programmable logic device comprising the steps of:

storing a plurality of slices of configuration data in a configuration memory on the programmable logic device, wherein each slice of configuration data provides a configuration for the programmable logic device; and

sequentially configuring the programmable logic device in an iterative manner using a subset of the slices of configuration data.

29. The method of claim 28, wherein the step of sequentially configuring the programmable logic device in an iterative manner is performed for a fixed number of cycles.

30. The method of claim 28, wherein the step of sequentially configuring the programmable logic device in an iterative manner is performed until a pre-determined condition is met.

31. A method of operating a programmable logic device in a logic engine mode, the method comprising the steps of:

configuring the programmable logic device in a first configuration by reading configuration data values from a first memory slice;

performing logic operations with the programmable logic device in the first configuration;

configuring the programmable logic device in a second configuration by reading configuration data values from a second memory slice; and

pipelining the read access time for the second memory slice such that the configuration data values from the second memory slice are read in parallel with the logic operations of the programmable logic device in the first configuration.

32. The method of claim 31, further comprising the step of accessing a third memory slice while the programmable logic device is performing logic operations in the first configuration.

33. The method of claim 32, wherein the third memory slice contains user data.

34. The method of claim 33, wherein the third memory slice contains configuration data.

35. The method of claim 32, wherein the step of accessing the third memory slice further comprises the step of reading data from the third memory slice.

36. The method of claim 32, wherein the step of accessing the third memory slice further comprises the step of writing data to the third memory slice.

37. The method of claim 32, further comprising the step of accessing a fourth memory slice while the programmable logic device is performing logic operations in the first configuration.

38. A programmable logic device comprising:

a first programming point for controlling the configuration of an interconnect of the programmable logic device;

a second programming point for controlling the configuration of a logic of the programmable logic device;

a first latch having an output terminal coupled to the first programming point, an input terminal coupled to a bit line, and a clock terminal coupled to receive a first clock signal;

a second latch having an output terminal coupled to the second programming point, an input terminal coupled to the bit line, and a clock terminal coupled to receive a second clock signal;

a first plurality of configuration memory cells coupled to the bit line and storing configuration data values for controlling the configuration of the interconnect;

a second plurality of configuration memory cells coupled to the bit line and storing configuration data values for controlling the configuration of the logic;

a first select circuit coupled between the bit line and the first plurality of configuration memory cells, wherein the first select circuit is controlled to couple one of the first plurality of configuration memory cells to the first latch during a first memory cycle; and

a second select circuit coupled between the bit line and the second plurality of configuration memory cells,

wherein the second select circuit is controlled to couple one of the second plurality of configuration memory cells to the second latch during a second memory cycle.

39. A method of configuring a programmable logic device comprising the steps of:

providing a first set of configuration memory cells for storing a first plurality of configuration data values for configuring an interconnect of the programmable logic device;

providing a second set of configuration memory cells for storing a second plurality of configuration data values for configuring an interconnect of the programmable logic device;

selectively coupling one of the configuration memory cells in the first set to a bit line during a first memory cycle;

latching a configuration data value from the bit line during the first memory cycle and providing this configuration data value to a first programming point to configure the interconnect of the programmable logic device;

selectively coupling one of the configuration memory cells in the second set to the bit line during a second memory cycle; and

latching a configuration data value from the bit line during the second memory cycle and providing this configuration data value to a second programming point to configure the logic of the programmable logic device.

40. A low voltage interconnect structure for an integrated circuit that operates in response to a supply voltage, the interconnect structure comprising:

an output circuit providing an output signal that swings between zero volts and a first voltage that is greater than zero volts and less than the supply voltage;

an interconnect circuit coupled to receive the output signal, the interconnect circuit comprising at least one turned on pass transistor; and

a destination circuit coupled to receive the output signal from the interconnect circuit.

41. The low voltage interconnect structure of claim 40, wherein the destination circuit comprises:

a first inverter circuit coupled to receive the output signal from the interconnect circuit, the first inverter circuit providing an output voltage that swings between zero volts and a second voltage that is greater than the first voltage and less than the supply voltage; and

a second inverter circuit coupled to the first inverter circuit, wherein the second inverter circuit provides an output voltage that swings between zero volts and the supply voltage.

42. A method for coupling an output circuit to a destination circuit on an integrated circuit, the method comprising the steps of:

providing an output signal with the output circuit that swings between zero volts and a first voltage that is greater than zero volts and less than the supply voltage;

routing the output signal through an interconnect circuit that comprises at least one turned on pass transistor; and

receiving the output signal with the destination circuit.

43. The method of claim 42, wherein the step of receiving the output signal comprises the step of receiving the output signal with a plurality of series-connected inverters, each inverter increasing the voltage of the output signal if the output signal has a logic high value.

44. The method of claim 43, wherein the inverters provide an output voltage equal to the supply voltage if the output signal has a logic high value.

46. The method of claim 44, wherein at least two of the sub-networks overlap.

47. The method of claim 46, further comprising the step of re-timing the input signals to a block in a first sub-network if the input signals do not all derive from the same clock signal.

48. The method of claim 47, wherein the re-timing is implemented by one or more flip-flops.

45. A method of operating a programmable logic device, the method comprising the steps of:

configuring the programmable logic device into a plurality of sub-networks; and

operating at least two of the sub-networks in response to asynchronous clock signals.

49. The method of claim 45, wherein the sub-networks are controlled by processes that are triggered by the asynchronous clock signals.

50. The method of claim 45, further comprising the steps of:

evaluating a first sub-network;

receiving a triggering signal for a second sub-network; and

placing the second sub-network in a waiting state until evaluation of the first sub-network is complete.

51. The method of claim 50, further comprising the step of implementing process scheduling in response to the asynchronous clock signals.

52. The method of claim 51, further comprising the step of implementing process scheduling in response to a high frequency clock signal generated by a phase locked loop.

53. The method of claim 50, wherein the triggering signal is derived from one or more of the asynchronous clock signals.

54. The method of claim 45, further comprising the steps of:

evaluating a first sub-network;

receiving a triggering signal for a second sub-network;

pre-empting the evaluation of the first sub-network and placing the first sub-network in a waiting state;

evaluating the second sub-network while the first sub-network is in the waiting state; and

then

completing the evaluation of the first sub-network.

55. The method of claim 45, further comprising the steps of:

storing intermediate states of each sub-network in a plurality of micro-registers; and

communicating between a first sub-network and a second sub-network by accessing micro-registers of the second sub-network with the first sub-network.

56. The method of claim 45, further comprising the steps of minimizing the number of sub-networks.