Bit line biasing method to eliminate program disturbance in a non-volatile memory device and memory device employing the same

• US 5,978,267 A
• Filed: 10/20/1998
• Issued: 11/02/1999
• Est. Priority Date: 10/20/1998
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Advanced Micro Devices, Inc., Fujitsu Limited
• Inventors: Hollmer, Shane C., Chung, Michael S. C., Le, Binh Quang, Leung, Vincent, Kawamura, Shoichi, Yano, Masaru, Chen, Pau-Ling, Van Buskirk, Michael
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): PHAN, TRONG Q
• Application Number:
  US09/175,647
• Time in Patent Office: 378 Days
• Field of Search: 365/185.17, 365/185.18, 365/185.23, 365/185.26, 365/185.33, 711/5
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

In the programming of a non-volatile memory device, such as a NAND flash memory device 100, a positive bias voltage V_bias is applied to a bit line 44 to set a respective memory gate 44a in a programmed state. In a further embodiment, the positive bias voltage V_bias is obtained by dividing the select drain gate voltage V_cc using two resistors 56 and 58 connected in series.

Claims

1. A method of programming a non-volatile memory device comprising a plurality of bit lines, a plurality of word lines, a select drain gate and a select source gate, the method comprising the steps of:

(a) applying a first word line voltage of about 20 V to a first one of the word lines, the first word line voltage representing a word program signal for a respective word on the first word line;

(b) applying a second word line voltage of about 10 V to a second one of the word lines, the second word line voltage representing a word program-inhibit signal for a respective word on the second word line;

(c) applying a bias voltage in the range of about 0.1 V to about 0.3 V to a first one of the bit lines for a respective first memory gate which is disposed on the first word line, to program the first memory gate with a logic bit representing a programmed state; and

(d) applying a select drain gate voltage to a second one of the bit lines for a respective second memory gate which is also disposed on the first word line such that the second memory gate maintains a logic bit representing a program-inhibited state.

2. The method of claim 1, wherein the bias voltage is about 0.2 V.

3. The method of claim 1, wherein the logic bit representing the program-inhibited state is logic bit 1 and the logic bit representing the programmed state is logic bit 0.

4. The method of claim 1, further comprising the step of applying a select source gate voltage of 0 V to the select source gate.

5. The method of claim 1, further comprising the step of dividing the select drain gate voltage by a predetermined ratio to obtain the bias voltage.

6. The method of claim 5, wherein the step of dividing the select drain gate voltage comprises the step of dividing the select drain gate voltage by a plurality of resistors to obtain the bias voltage.

7. The method of claim 6, wherein the plurality of resistors comprise first and second resistors connected in series, the first resistor connected to the select drain gate voltage and the second resistor connected to ground, the bias voltage obtained from an intermediate position between the first and second resistors, the first and second resistors having first and second resistances, respectively, and the ratio of the second resistance to the sum of the first and second resistances being equal to the predetermined ratio of the bias voltage to the select drain gate voltage.

8. The method of claim 1, wherein the non-volatile memory device comprises a NAND non-volatile memory device, and the first and second memory gates comprise first and second NAND gates, respectively.

9. The method of claim 1, further comprising the step of applying the select drain gate voltage to the select drain gate.

10. The method of claim 9, wherein the select drain gate voltage is about 3.3 V.