Charge pump circuits

• US 5,978,283 A
• Filed: 07/02/1998
• Issued: 11/02/1999
• Est. Priority Date: 07/02/1998
• Status: Expired due to Fees

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Aplus Flash Technology, Inc.
• Inventors: Lee, Peter Wung, Tsao, Hsing-Ya, Hsu, Fu-Chang
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US09/109,652
• Time in Patent Office: 488 Days
• Field of Search: 365/189.09, 365/226, 327/534, 327/536, 327/537
• US Class Current: 365/189.09
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type

Abstract

Charge pump circuits for stepping up high voltages for flash memory array are disclosed. A first circuit comprises a plurality of series-coupled charge pumps having pump capacitors connected to each pump stage. A first group of charge pumps of the pump circuit are AC coupled through pump capacitors to two non-overlapping pulse trains. To reduce the high voltage that a pump capacitor has to withstand, each pump capacitor after the first group is connected to an earlier pump stage instead of the non-overlapping pulse trains. Therefore, the charge pump circuit can output voltage higher than the breakdown voltage of the pump capacitors. A second circuit comprising a configurable charge pump circuit is also presented. By connecting selected pump stages through diode paths to the output of the charge pump circuit and having a plurality of pulse train inputs, the charge pump circuit can be configured as a high voltage low current charge pump or a low voltage high current charge pump dependent on how pulse train signals are provided to the pulse train inputs. Finally, an improved structure for pump capacitors used in the charge pump circuit is presented.

Claims

1. A charge pump circuit comprising:

two pulse train inputs providing two non-overlapping pulse train signals;

a first group of N series-coupled pump stages having at least two pump stages, each pump stage of said first group including a MOS device, a node and a pump capacitor having a first end connected to said node and a second end connected to one of said pulse train inputs, wherein adjacent pump stages have pump capacitors connecting to different pulse train inputs; and

a second group of series-coupled pump stages series-coupled to said first group, each pump stage of said second group including a MOS device, a node and a pump capacitor having a first end connected to said node and a second end connected to the node of a preceding pump stage that is N stage away in said charge pump circuit, said second group having at least one pump stage.

2. The charge pump circuit according to claim 1, wherein said first group has an even number of series-coupled pump stages.

3. The charge pump circuit according to claim 1, wherein the node of each pump stage is further connected through a MOS device to a power supply voltage.

4. The charge pump circuit according to claim 1, wherein the pump capacitor connected to each node comprises a floating gate, a well region formed in a substrate, and two diffusion regions serving as a drain and a source formed in said well region, said substrate and said well region having different doping types and said drain and source being connected together.

16. The charge pump circuit according to claim 1, wherein the pump capacitor connected to each node comprises a floating gate, a first well region formed within a second well region formed in a substrate, and two diffusion regions serving as a drain and a source formed in said first well region, said substrate and said first well region having a first doping type, said second well region having a second doping type, and said drain and source being connected together.

5. A charge pump circuit comprising:

N pulse train inputs providing N pulse train signals;

a first group of N series-coupled pump stages, each pump stage of said first group including a MOS device, a node and a pump capacitor having a first end connected to said node and a second end connected to one of said N pulse train inputs, wherein each node is AC coupled to a different pulse train input and the node of every even stage is further connected through a MOS device to the output of said pump circuit; and

a second group of N series-coupled pump stages series-coupled to said first group, each pump stage of said second group including a MOS device, a node and a pump capacitor having a first end connected to said node and a second end connected to one of said N pulse train inputs, wherein each node is AC coupled to a different pulse train input and the node of every even stage is further connected through a MOS device to the output of said pump circuit;

wherein the first nodes of said first and second groups are AC coupled to a first pulse train input, the second nodes of said first and second groups are AC coupled to a second pulse train input, the third nodes of said first and second groups are AC coupled to a third pulse train input, and so on.

6. The charge pump circuit according to claim 5, wherein N is a power of 2.

7. The charge pump circuit according to claim 5, wherein the node of each pump stage is further connected through a MOS device to a power supply voltage.

8. The charge pump circuit according to claim 5, said pump circuit being built in an integrated circuit and configurable as either a higher voltage charge pump or a lower voltage charge pump for a flash memory array by providing appropriate pulse train signals to said pulse train inputs.

9. The charge pump circuit according to claim 5, wherein the pump capacitor connected to each node comprises a floating gate, a well region formed in a substrate, and two diffusion regions serving as a drain and a source formed in said well region, said substrate and said well region having different doping types and said drain and source being connected together.

17. The charge pump circuit according to claim 5, wherein the pump capacitor connected to each node comprises a floating gate, a first well region formed within a second well region formed in a substrate, and two diffusion regions serving as a drain and a source formed in said first well region, said substrate and said first well region having a first doping type, said second well region having a second doping type, and said drain and source being connected together.

10. A charge pump circuit comprising:

N pulse train inputs providing N pulse train signals; and

N series-coupled pump stages, each pump stage including a MOS device, a node and a pump capacitor having a first end connected to said node and a second end connected to one of said N pulse train inputs;

wherein each node is AC coupled to a different pulse train input and each node of the first N-1 pump stages of said pump circuit is further connected through a MOS device to the output of said pump circuit.

11. The charge pump circuit according to claim 10, wherein the node of each pump stage is further connected through a MOS device to a power supply voltage.

12. The charge pump circuit according to claim 10, wherein the pump capacitor connected to each node comprises a floating gate, a well region formed in a substrate, and two diffusion regions serving as a drain and a source formed in said well region, said substrate and said well region having different doping types and said drain and source being connected together.

13. The charge pump circuit according to claim 10, said pump circuit being built in an integrated circuit and configurable as either a higher voltage charge pump or a lower voltage charge pump for a flash memory array by providing appropriate pulse train signals to said pulse train inputs.

14. The charge pump circuit according to claim 10, wherein the node of the last pump stage of said pump circuit is also connected through a MOS device to the output of said pump circuit.

15. The charge pump circuit according to claim 14, wherein the node of each pump stage is further connected through a MOS device to a power supply voltage.

18. The charge pump circuit according to claim 10, wherein the pump capacitor connected to each node comprises a floating gate, a first well region formed within a second well region formed in a substrate, and two diffusion regions serving as a drain and a source formed in said first well region, said substrate and said first well region having a first doping type, said second well region having a second doping type, and said drain and source being connected together.