Sequential access memories

• US 5,978,295 A
• Filed: 06/30/1998
• Issued: 11/02/1999
• Est. Priority Date: 07/04/1997
• Status: Expired due to Term

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Pomet, Alain, Plessier, Bernard
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US09/106,941
• Time in Patent Office: 490 Days
• Field of Search: 365/78, 365/189.12, 365/221, 365/239, 365/240
• US Class Current: 365/221
• CPC Class Codes: G11C 19/00 Digital stores in which the information is moved stepwise, e.g. shift registers
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A sequential access memory comprises N register elements each storing an information bit. These N register elements are divided into P groups each comprising L elements. In a first phase of operation whose duration corresponds to P-1 consecutive periods of the clock signal, only the last elements of each group are activated and are furthermore series-connected. In a second phase of operation whose duration corresponds to a single period of the clock signal, all the elements are activated simultaneously, the groups of elements being furthermore series-connected. The advantage is that it enables a reduction in the dynamic consumption of the memory.

Claims

1. A sequential access memory working at a rate of a clock signal and comprising:

N bistable and synchronous register elements, each storing an information bit, the N elements being divided into P groups each comprising L elements; and

a management unit for causing the elements to operate as follows

in a first phase of operation whose duration corresponds to P-1 consecutive periods of the clock signal, only last elements of each group are activated simultaneously and are furthermore series-connected, an input of a first of these elements then defining an input of the memory and an output of a last element then defining an output of the memory, and

in a second phase of operation whose duration corresponds to a single period of the clock signal, all the elements are activated, the groups of elements being furthermore series-connected, the input of the first element of the first group then defining the input of the memory, and the output of the last element of the last group then defining the output of the memory.

2. A memory according to claim 1, further comprising selection means operatively connected between an output of a second-to-last element and an input of the last element of each group.

3. A memory according to claim 2, wherein said selection means is controlled by the management unit for making the memory operate alternately in the first phase of operation and in the second phase of operation.

4. A memory according to claim 3, wherein said selection means comprises:

a first input connected to the output of the second-to-last element of the group concerned;

a second input which, for a first group of elements, receives the data elements entering the memory which are furthermore transmitted to the input of the first element of the group and, for the other groups, is connected to the output of the last element of the previous group, this output being furthermore connected to the input of the first element of the group concerned; and

an output connected to the input of the last element of the group concerned, the state of said output being equal either to the state of said first input or to the state of said second input as a function of the state of a third input.

5. A memory according to claim 2, wherein said selection means comprises at least one two-channel multiplexer.

6. A sequential access memory comprising:

N bistable and synchronous register elements, each storing an information bit, the N elements being divided into P groups each comprising L elements;

a management unit for causing the elements to operate as follows

in a first phase of operation whose duration corresponds to P-1 consecutive periods of a clock signal, only last elements of each group are activated simultaneously and are furthermore series-connected, an input of a first of these elements then defining an input of the memory and an output of a last element then defining an output of the memory, and

in a second phase of operation whose duration corresponds to a single period of the clock signal, all the elements are activated, the groups of elements being furthermore series-connected, the input of the first element of the first group then defining the input of the memory, and the output of the last element of the last group then defining the output of the memory; and

a selection circuit cooperating with said management unit for making the memory operate alternately in the first phase of operation and in the second phase of operation.

7. A memory according to claim 6, wherein said selection circuit is operatively connected between an output of a second-to-last element and an input of the last element of each group.

8. A memory according to claim 7, wherein said selection circuit comprises:

a first input connected to the output of the second-to-last element of the group concerned;

a second input which, for a first group of elements, receives the data elements entering the memory which are furthermore transmitted to the input of the first element of the group and, for the other groups, is connected to the output of the last element of the previous group, this output being furthermore connected to the input of the first element of the group concerned; and

an output connected to the input of the last element of the group concerned, the state of said output being equal either to the state of said first input or to the state of said second input as a function of the state of a third input.

9. A memory according to claim 6, wherein said selection circuit comprises at least one two-channel multiplexer.

10. A sequential access memory comprising:

N bistable and synchronous register elements, each storing an information bit, the N elements being divided into P groups each comprising L elements; and

a management unit for causing the elements to operate in alternate first and second phases of operation as follows

in the first phase of operation whose duration corresponds to P-1 consecutive periods of the clock signal, only last elements of each group are activated simultaneously and are furthermore series-connected, an input of a first of these elements then defining an input of the memory and an output of a last element then defining an output of the memory, and

in the second phase of operation whose duration corresponds to a single period of the clock signal, all the elements are activated, the groups of elements being furthermore series-connected, the input of the first element of the first group then defining the input of the memory, and the output of the last element of the last group then defining the output of the memory.

11. A memory according to claim 10, further comprising selection means operatively connected between an output of a second-to-last element and an input of the last element of each group.

12. A memory according to claim 11, wherein said selection means is controlled by the management unit for making the memory operate alternately in the first phase of operation and in the second phase of operation.

13. A memory according to claim 11, wherein said selection means comprises:

a first input connected to the output of the second to last element of the group concerned;

a second input which, for a first group of elements, receives the data elements entering the memory which are furthermore transmitted to the input of the first element of the group and, for the other groups, is connected to the output of the last element of the previous group, this output being furthermore connected to the input of the first element of the group concerned; and

an output connected to the input of the last element of the group concerned, the state of said output being equal either to the state of said first input or to the state of said second input as a function of the state of a third input.

14. A memory according to claim 13, wherein said selection means comprises at least one two-channel multiplexer.

15. A method for operating a sequential access memory working at a rate of a clock signal and comprising N bistable and synchronous register elements, each storing an information bit, the N elements being divided into P groups each comprising L elements, the method comprising the steps of:

in a first phase of operation whose duration corresponds to P-1 consecutive periods of the clock signal, only last elements of each group are activated simultaneously and being furthermore series-connected, so that an input of a first of these elements then defines an input of the memory and an output of a last element then defines an output of the memory; and

in a second phase of operation whose duration corresponds to a single period of the clock signal, all the elements are activated, the groups of elements being furthermore series-connected, the input of the first element of the first group then defines the input of the memory, and the output of the last element of the last group then defines the output of the memory.

16. A method according to claim 15, further comprising the step of making the memory operate alternately in the first phase of operation and in the second phase of operation.