Semiconductor integrated circuit device
First Claim
1. A semiconductor integrated circuit device comprising:
- a plurality of mats; and
a control circuit which is commonly provided for said plurality of mats;
said plurality of mats each including,a memory array;
an arithmetic circuit which adds a predetermined value to an input address signal or subtracts the same therefrom to form an output address signal; and
a comparator which determines coincidence or non-coincidence between either one of the input address signal or the output address signal and a mat selection signal commonly supplied to said plurality of mats; and
wherein a plurality of said arithmetic circuits corresponding to said plurality of mats are connected in cascade form, anda corresponding memory array lying within a mat corresponding to said comparator having determined coincidence or non-coincidence is activated when the result of determination by said comparator shows a coincidence.
2 Assignments
0 Petitions
Accused Products
Abstract
A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or -1 arithmetic operations are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.
23 Citations
26 Claims
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1. A semiconductor integrated circuit device comprising:
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a plurality of mats; and a control circuit which is commonly provided for said plurality of mats; said plurality of mats each including, a memory array; an arithmetic circuit which adds a predetermined value to an input address signal or subtracts the same therefrom to form an output address signal; and a comparator which determines coincidence or non-coincidence between either one of the input address signal or the output address signal and a mat selection signal commonly supplied to said plurality of mats; and wherein a plurality of said arithmetic circuits corresponding to said plurality of mats are connected in cascade form, and a corresponding memory array lying within a mat corresponding to said comparator having determined coincidence or non-coincidence is activated when the result of determination by said comparator shows a coincidence. - View Dependent Claims (2, 3)
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4. A semiconductor integrated circuit device comprising:
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a plurality of unit circuits respectively including, memory arrays; arithmetic circuits; and determination circuits, and wherein each arithmetic circuit adds a predetermined value to a signal inputted thereto or subtracts the same therefrom, said plurality of arithmetic circuits in said plurality of unit circuits are connected in cascade form such that signals outputted from said respective arithmetic circuits are set as input signals for the following-stage arithmetic circuits, said determination circuit determines coincidence or non-coincidence between either one of an input signal or an output signal of the corresponding arithmetic circuit and a selection signal commonly supplied to said plurality of unit circuits, and when the result of determination by said determination circuit shows a coincidence, the corresponding memory array lying within the unit circuit corresponding to said determination circuit having determined coincidence or non-coincidence is activated. - View Dependent Claims (5, 6)
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7. A semiconductor integrated circuit device comprising:
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a plurality of unit circuits each including, an internal circuit block; an arithmetic circuit; and a comparator; and wherein said each arithmetic circuit adds a predetermined value to a signal inputted thereto or subtracts the same therefrom, said plurality of arithmetic circuits in said plurality of unit circuits are connected in cascade form such that signals outputted from said respective arithmetic circuits are set as input signals for the following-stage arithmetic circuits, said comparator determines coincidence or non-coincidence between either one of an input signal or an output signal of the corresponding arithmetic circuit and a selection signal commonly supplied to said plurality of unit circuits, and when the result of determination by said comparator shows a coincidence, the corresponding internal circuit block lying within the unit circuit corresponding to said comparator having determined coincidence or non-coincidence is activated. - View Dependent Claims (8, 9)
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10. A semiconductor integrated circuit device comprising:
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a RAM module including, a plurality of memory mats each including a memory array; and a control circuit commonly provided for said plurality of memory mats; said memory array including a plurality of word lines, a plurality of bit lines and a plurality of memory cells, said plurality of memory mats each including, an arithmetic circuit which performs +1 or -1 arithmetic operations on each of address-setting input signals comprised of a plurality of bits; and a comparator which determines whether an input signal supplied to said arithmetic circuit or a signal outputted from said arithmetic circuit coincides with an address signal inputted upon memory access, and wherein said arithmetic circuits in said plurality of memory mats are connected in cascade form, and each memory mat activates an address selecting operation according to a signal indicative of the coincidence. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A semiconductor integrated circuit device comprising:
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a plurality of circuit blocks each having a specific circuit function, said respective circuit blocks including, arithmetic circuits which are respectively provided in said respective circuit blocks and perform +1 or -1 arithmetic operations on address-setting input signals comprised of a plurality of bits; and comparators which respectively determine coincidences between input signals supplied to said arithmetic circuits or output signals produced therefrom and address signals, and wherein the arithmetic circuits in said plurality of circuit blocks are connected in cascade form, the arithmetic circuit in the initial-stage circuit block has an input terminal supplied with fixed address signals, and the corresponding circuit block in respective circuit blocks is activated when a coincidence signal is outputted from said each comparator.
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Specification