Hybrid phase-locked loop employing analog and digital loop filters

• US 5,978,425 A
• Filed: 05/23/1997
• Issued: 11/02/1999
• Est. Priority Date: 05/23/1997
• Status: Expired due to Term

• Current Assignee: Renesas Electronics America Inc.(f/k/a Integrated Device Technology, Inc) (Renesas Electronics Corporation)
• Original Assignee: Hitachi Micro Systems, Inc. (Hitachi, Ltd.)
• Inventors: Takla, Ashraf K.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): JIANG, LENNY R
• Application Number:
  US08/863,039
• Time in Patent Office: 893 Days
• Field of Search: 375/374, 375/376, 375/375, 375/371, 375/373, 331/1 A, 331/14, 331/10, 331/17, 331/1 R, 327/156, 327/157, 327/159
• US Class Current: 375/374
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence

Abstract

The invention provides a hybrid phase-locked loop (PLL) containing digital and analog portions for digital and analog adjustments, respectively, of an output signal. The hybrid PLL is simple in design. Off-the-shelf controlled oscillators, such as a current controlled oscillator (CCO) can be used with this hybrid PLL. The digital and the analog portions of the hybrid PLL are separate from the controlled oscillator. The digital portion is for a first adjustment of the frequency of the output signal, such as during a calibration. The analog portion is for fine phase and frequency adjustment of the output signal.

Claims

1. A phase-locked loop comprising:

a detector;

a digital loop filter coupled to the detector, the digital loop filter including a digital filter and a successive approximation register which is responsive to the digital filter;

a digital-to-analog converter coupled to the digital loop filter;

a variable oscillator coupled to the digital-to-analog converter; and

an analog filter coupled between the detector and the variable oscillator, wherein the analog filter is enabled when the digital filter is disabled.

2. The phase-locked loop of claim 1,

wherein the digital filter includes an output port and a first divider, a second divider, and a third divider, each divider coupled to the output port of the digital filter, each divider, having a reset port, the output port of the digital filter coupled to each reset port of the first, second, and third dividers,

wherein the detector includes a first output port and a second output port, and

wherein the first divider is coupled to the first output port of the detector, the second divider is coupled to the first and second output ports of the detector, the third divider is coupled to the second output port of the detector.

3. The phase-locked loop of claim 2, wherein the digital filter includes a delay circuit coupled between the output port of the digital filter and each reset port of the first, second, and third dividers.

4. The phase-locked loop of claim 1, wherein the variable oscillator is a current controlled oscillator, the phase-locked loop further comprising a voltage-to-current converter coupled between the filter and the current controlled oscillator.

5. The phase-locked loop of claim 1, wherein the detector comprises a phase detector.

6. The phase-locked loop of claim 1, wherein the detector comprises a phase-frequency detector, the phase-locked loop further comprising a pulse gate coupled between the phase-frequency detector and the variable oscillator.

7. The phase-locked loop of claim 1, wherein the filter is an analog filter, the phase-locked loop further comprising a charge pump coupled between the detector and the analog filter.

8. The phase-locked loop of claim 1, further comprising:

a first multiplexer coupled to the detector, the multiplexer including a data port and a training port;

a second multiplexer coupled between the detector and the variable oscillator, the second multiplexer having a first input and a second input, the first input of the second multiplexer coupled to the variable oscillator;

a first divider coupled to the training port of the first multiplexer; and

a second divider coupled between the variable oscillator and the second input port of the second multiplexer.

9. The phase-locked loop of claim 1, further comprising a control circuit coupled to the detector, to the digital loop filter, and to the digital-to-analog converter.

10. A method for acquiring phase-lock comprising the steps of:

coupling a data signal to a detector;

coupling an output signal to the detector;

comparing the phase of the data signal with the phase of the output signal;

generating a comparison signal based on the phase comparison of the data signal and the output signal;

providing an analog filter coupled to the detector to receive the comparison signal;

providing a digital filter coupled to the detector to receive the comparison signal;

transforming the comparison signal into a successive digital approximation signal, wherein the successive approximation signal is maintained at a level which disables the analog filter when the digital filter is enabled; and

transforming the comparison signal into a fine adjustment signal.

11. The method of claim 10, wherein the digital approximation signal is a current ranging between approximately 50 and 500 micro-amperes.

12. The method of claim 10, wherein the step of transforming into a fine adjustment signal includes transforming into an analog signal.

13. The method of claim 12, wherein the analog signal is a current of approximately up to 50 micro-amperes.

14. The method of claim 10, wherein the step of transforming the comparison signal into a digital approximation signal includes the step of counting the times when the output signal lags in phase behind the data signal and the times that the output signal is ahead in phase of the data signal.

15. A program storage device readable by a machine for communicating with a detector for coupling a data signal, tangibly embodying a program of instructions executable by the machine to perform method steps for acquiring phase-lock, said method steps comprising:

coupling a data signal to a detector;

coupling an output signal to the detector;

comparing the phase of the data signal with the phase of the output signal;

generating a comparison signal based on the phase comparison of the data signal and the output signal;

coupling an analog filter to the detector to receive the comparison signal;

coupling a digital filter to the detector to receive the comparison signal;

transforming the comparison signal into a successive digital approximation signal, wherein the successive approximation signal is maintained at a level which disables the analog filter when the digital filter is enabled; and

transforming the comparison signal into a fine adjustment signal.

16. An apparatus for acquiring phase-lock comprising:

means for coupling a data signal to a detector;

means for coupling an output signal to the detector;

means for comparing the phase of the data signal with the phase of the output signal;

means for generating a comparison signal based on the phase comparison of the data signal and the output signal;

an analog filter means coupled to the detector for filtering the comparison signal;

a digital filter means coupled to the detector for filtering the comparison signal;

means for transforming the comparison signal into a successive digital approximation signal, wherein the successive approximation signal is maintained at a level which disables the analog filter means when the digital filter means is enabled; and

means for transforming the comparison signal into a fine adjustment signal.

17. An apparatus according to claim 16, in which the means for transforming the comparison signal to the successive digital approximation signal includes a digital filter and a successive approximation register which is responsive to the digital filter.

18. A phase-locked loop comprising:

a phase-frequency detector;

a digital loop filter coupled to the phase-frequency detector including a digital filter and a successive approximation register, the successive approximation register being responsive to the digital filter;

a digital-to-analog converter coupled to the digital loop filter;

a variable oscillator coupled to the digital-to-analog converter, wherein the digital filter commands the successive approximation register to produce a successive digital approximation signal for controlling the variable oscillator; and

an analog filter coupled to the phase-frequency detector and to the variable oscillator, wherein the analog filter is enabled when the digital filter is disabled.

19. A phase-locked loop according to claim 18, the phase-locked loop further including a control circuit coupled to the digital loop filter and the digital-to-analog converter, the control circuit being responsive to the phase-frequency detector, wherein the digital loop filter and the digital-to-analog converter are activated by the control circuit when the phase-locked loop is in calibration mode and when the phase-locked loop loses phase-frequency lock.

20. A method for acquiring phase-lock comprising the steps of:

coupling a data signal to a detector;

coupling an output signal to the detector;

comparing the phase of the data signal with the phase of the output signal;

generating a comparison signal based on the phase comparison of the data signal and the output signal;

analog filtering the comparison signal with an analog filter;

digitally filtering the comparison signal with a digital filter;

transforming the digitally filtered comparison signal into a successive digital approximation signal, wherein the successive approximation signal is maintained at a level that disables the analog filter when the digital filter is enabled; and

transforming the comparison signal into a fine adjustment signal, wherein each of the successive digital approximation signal and the fine adjustment signal control a variable oscillator for producing the output signal.