Video decompression and decoding system utilizing control and data tokens

• US 5,978,592 A
• Filed: 10/08/1997
• Issued: 11/02/1999
• Est. Priority Date: 06/30/1992
• Status: Expired due to Term

• Current Assignee: Coases Investments Bros LLC (Intellectual Ventures LLC)
• Original Assignee: Discovision Associates (Pioneer Corporation)
• Inventors: Wise, Adrian Philip
• Primary Examiner(s): An, Meng-Ai T.
• Assistant Examiner(s): Davis, Jr., Walter D.
• Application Number:
  US08/947,676
• Time in Patent Office: 755 Days
• Field of Search: 395/800.01, 395/888, 395/376, 395/800.18, 341/50, 341/65, 341/67, 348/384, 348/403, 348/405
• US Class Current: 712/1
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/4494 data driven
• CPC Class Codes: H04N 19/13 Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/44 Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Abstract

A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Claims

1. In a video decompression and decoding system having an input, an output and a plurality of pipelined processing stages between the input and the output, the improvement comprising:

said pipelined processing stages comprising;

a start code detector connected to said input;

a Huffman decoder coupled to said start code detector;

an index-to-data unit coupled to said Huffman decoder;

an arithmetic logical unit coupled to said index-to-data unit;

a token formatter receiving data from said arithmetic logical unit;

an inverse modeler coupled to said token formatter;

an inverse quantizer coupled to said inverse modeler;

an inverse zig-zag unit coupled to said inverse quantizer;

an inverse discrete cosine transform module coupled to said inverse zig-zag unit;

a temporal decoder coupled to said inverse discrete cosine transform module and

an interactive interfacing control token having a variable length, defining a universal adaptation unit for control and/or data functions among said processing stages, wherein said token comprises a plurality of data words, each said word including an extension bit which indicates a presence or an absence of additional words in said token, said length of said token being determined by said extension bits;

whereby said processing stages are afforded enhanced flexibility in the performance of diverse tasks.

2. The system as recited in claim 1, wherein said token is position independent of said processing stages for performance of functions.

3. The system as recited in claim 1, wherein said control token causes said processing stages to reconfigure.

4. The system as recited in claim 1, wherein said token has an address field which characterizes said token.

5. The system as recited in claim 4, wherein interaction with a selected processing stage is determined by said address field.

6. The system as recited in either claim 4 or 5, wherein said token comprises a succession of tokens, and a said address field of a first token of said succession differs in length from a said address field of a succeeding token.

7. The system as recited in any of claims 4 or 5, wherein said address field is Huffman coded.

8. The system as recited in claim 1, wherein said control token is devoid of data.

9. The system as recited in claim 1, wherein said control token only conditions said processing stages.

10. The system as recited in claim 9, wherein the conditioning includes reconfiguring of said processing stages.

11. The system as recited in claim 1, wherein said control token identifies a coding standard to said processing stages.

12. A system as recited in claim 1, Wherein certain of said control tokens carry control bits containing indices indicating information for use in corresponding state machines to create a set of picture standard-independent indexer signals.

15. The system as recited in either claim 1 or 13 wherein said token is generated by one of said processing stages.

16. The system as recited in either claim 1 or 13 wherein said token is converted by one of said processing stages.

17. The system as recited in either claim 1 or 13 wherein said token is dynamically adaptive.

18. The system as recited in either claim 1 or 13 wherein said token is altered by interfacing with said stages.

19. The system as recited in either claim 1 or 13 wherein said token interacts with all of said stages.

20. The system as recited in either claim 1 or 13 wherein said token interacts with some, but less than all of said stages.

21. The system as recited in either claim 1 or 13 wherein said token interacts with only predetermined ones of said stages.

22. The system as recited in either claim 1 or 13, wherein said token interacts with adjacent stages.

23. The system as recited in either claim 1 or 13, wherein said token interacts with non-adjacent stages.

24. The system as recited in either claim 1 or 13, wherein said token is position dependent for some functions and position independent for other functions.

25. The system as recited in either claim 1 or 13, wherein the interaction of said token with a stage is conditioned by the previous processing history of said stage.

27. The system as recited in either claim 1 or 13, wherein said token is hybrid control and DATA token and provides both data and conditioning to said processing stages.

28. The system as recited in either claim 1 or 13, wherein said token operates independent of any coding standard among said processing stages.

29. The system as recited in either claim 1 or 13, wherein said token is capable of successive alteration by said processing stages.

30. The system as recited in either claim 1 or 13, wherein said token provides data and control simultaneously to a processing stage.

31. The system as recited in either claim 1 or 13, wherein said system operates on a data stream containing a mixture of data according to an MPEG, JPEG and an H.261 coding standard.

13. In a video decompression and decoding system having an input, an output and a plurality of pipelined processing stages between the input and the output, the improvement comprising:

said pipelined processing stages comprising;

a start code detector connected to said input;

a Huffman decoder coupled to said start code detector;

an index-to-data unit coupled to said Huffman decoder;

an arithmetic logical unit coupled to said index-to-data unit;

a token formatter receiving data from said arithmetic logical unit;

an inverse modeler coupled to said token formatter;

an inverse quantizer coupled to said inverse modeler;

an inverse zig-zag unit coupled to said inverse quantizer;

an inverse discrete cosine transform module coupled to said inverse zig-zag unit;

a temporal decoder coupled to said inverse discrete cosine transform module; and

an interactive metamorphic interfacing data token having a variable length, defining a universal adaptation unit for data functions among said processing stages, wherein said token comprises a plurality of data words, each said word including an extension bit which indicates a presence or an absence of additional words in said token, said length of said token being determined by said extension bits;

whereby said processing stages are afforded enhanced flexibility in the processing of data.

14. The system as recited in claim 13 wherein said token is position dependent upon said processing stages for its performance.

26. The system as recited in claim 13, wherein said DATA token includes data for transfer to said processing stages.