Packet protocol and distributed burst engine
First Claim
1. An apparatus for communicating with a host processor and a device, the host having a memory for storing at least one pool of packets, each pool comprised of a linked list of packets, each packet having a header including a physical address field for containing a physical address of a next packet to form the linked list, the apparatus comprising:
- a request head register operable to hold the physical address of a next packet of the linked list;
a free queue register operable to hold the physical address of the last packet of the linked list;
a request queue for holding packets, said request queue operable to provide a fullness indication when a packet is therein;
a request doorbell register operable to receive an indication from the host that a next packet is available to process;
a completion head register operable to hold the physical address of a completion list;
a completion queue for holding packets;
a completion doorbell register operable to receive an indication from the host that said completion queue has been serviced and that the host is ready to receive packets;
a first front end controller coupled to the request queue and responsive to said request doorbell register, said first front end controller operable to read a packet from memory according to the physical address stored in the request head register when said request doorbell register is rung and store the packet in said request queue;
a first back end controller coupled to the request queue and the completion queue and responsive to the request queue fullness indication, said first back end controller operable to read a packet from said request queue when said request queue is not empty and provide the packet to the device, said first back end controller further operable to provide the packet to said completion queue when the device has completed processing the packet; and
a completion controller coupled to said completion queue and responsive to the completion doorbell register and the completion head register, said completion controller operable to complete a packet from the completion queue back to the memory.
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Accused Products
Abstract
A method and apparatus for decoupling input/output (I/O) from host processing through main memory. A command packet architecture and distributed burst engine for communicating data to an I/O device without using memory mapped I/O or host processor synchronization. The packet architecture includes a header having fields for linking packets in a list with physical and virtual addresses, thereby eliminating address translations. The distributed burst engine includes buffers and controllers for bursting the linked lists of packets between main memory and the I/O device. Doorbell registers are included for the host processor to indicate to the DBE that an event has occurred. The distributed burst engine is versatile enough to be bus independent and located virtually anywhere between main memory and the I/O device.
60 Citations
34 Claims
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1. An apparatus for communicating with a host processor and a device, the host having a memory for storing at least one pool of packets, each pool comprised of a linked list of packets, each packet having a header including a physical address field for containing a physical address of a next packet to form the linked list, the apparatus comprising:
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a request head register operable to hold the physical address of a next packet of the linked list; a free queue register operable to hold the physical address of the last packet of the linked list; a request queue for holding packets, said request queue operable to provide a fullness indication when a packet is therein; a request doorbell register operable to receive an indication from the host that a next packet is available to process; a completion head register operable to hold the physical address of a completion list; a completion queue for holding packets; a completion doorbell register operable to receive an indication from the host that said completion queue has been serviced and that the host is ready to receive packets; a first front end controller coupled to the request queue and responsive to said request doorbell register, said first front end controller operable to read a packet from memory according to the physical address stored in the request head register when said request doorbell register is rung and store the packet in said request queue; a first back end controller coupled to the request queue and the completion queue and responsive to the request queue fullness indication, said first back end controller operable to read a packet from said request queue when said request queue is not empty and provide the packet to the device, said first back end controller further operable to provide the packet to said completion queue when the device has completed processing the packet; and a completion controller coupled to said completion queue and responsive to the completion doorbell register and the completion head register, said completion controller operable to complete a packet from the completion queue back to the memory. - View Dependent Claims (2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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7. The apparatus of claim 7, wherein the packets are characterized as being asynchronous, polled and interrupt packets, and wherein if the completed packet is an interrupt packet said completion controller is further operable to cause an interrupt to the host after clearing said completion doorbell register.
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18. A computer system having automatic direct memory access, the computer system comprising:
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a main memory for storing at least one pool of packets, each pool comprised of a linked list of packets, each packet having a header including a physical address field for containing a physical address of a next packet to form the linked list; a processor coupled to said main memory; a mass storage subsystem; a distributed burst engine coupled between said mass storage subsystem and said main memory, the distributed burst engine comprising; a request head register operable to hold the physical address of a next packet of the linked list; a free queue register operable to hold the physical address of the last packet of the linked list; a request queue for holding packets, said request queue operable to provide a fullness indication when a packet is therein; a request doorbell register operable to receive an indication from the host that a next packet is available to process; a completion head register operable to hold the physical address of a completion list; a completion queue for holding packets; a completion doorbell register operable to receive an indication from the processor that said completion queue has been serviced and that the processor is ready to receive packets; a first front end controller coupled to the request queue and responsive to said request doorbell register, said first front end controller operable to read a packet from memory according to the physical address stored in the request head register when said request doorbell register is rung and store the packet in said request queue; a first back end controller coupled to the request queue and the completion queue and responsive to the request queue fullness indication, said first back end controller operable to read a packet from said request queue when said request queue is not empty and provide the packet to the mass storage subsystem, said first back end controller further operable to provide the packet to said completion queue when the mass storage subsystem has completed processing the packet; and a completion controller coupled to said completion queue and responsive to the completion doorbell register and the completion head register, said completion controller operable to complete a packet from the completion queue back to the memory. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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Specification