Host adaptor comprising a status switching circuit which couples an output line to a function input line in response to a function enable line signal

• US 5,978,863 A
• Filed: 06/09/1997
• Issued: 11/02/1999
• Est. Priority Date: 09/07/1994
• Status: Expired due to Term

• Current Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Original Assignee: Adaptec Incorporated (Steel Partners Holdings LP)
• Inventors: Fannin, Charles S., Gates, Stillman F.
• Primary Examiner(s): An, Meng-Ai T.
• Assistant Examiner(s): YUAN, CHIEN H
• Application Number:
  US08/876,539
• Time in Patent Office: 876 Days
• Field of Search: 379/93.32, 388/813, 710/100, 710/107, 710/127
• US Class Current: 710/18
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
• CPC Class Codes: G06F 13/126 and has means for transferring I/O instructions and statuses between control unit and main processor

Abstract

A host adapter for transferring data between a system bus and an input/output (I/O) bus is implemented as an integrated circuit having a data transfer circuit and a status indicator circuit. The status indicator circuit selectively supplies one of a number of status signals from the data transfer circuit as a signal on a status indicator terminal of the host adapter. Therefore, a light emitting diode connected to the status indicator terminal indicates in real time the status of data transfer, such as usage of the system bus, or I/O bus, or execution time of one or more instructions by the host adapter.

Claims

1. A method of operating a status switching circuit having a plurality of input lines, an output line and a disable line, said method comprising;

driving a signal on a first input line in said plurality of input lines based on the value of an input storage unit in a status storage element;

detecting an active signal on said disable line;

setting the value of said input storage unit in said status storage element;

disconnecting an output line of said status switching circuit from every one of said input lines;

detecting an inactive signal on said disable line; and

connecting said output line to said first input line.

2. The method of claim 1 further comprising:

detecting the use of a bus connected to a host adapter that includes said status storage element; and

driving a signal on a second input line of said status switching circuit in response to said step of detecting the use.

3. The method of claim 2, wherein said status storage element includes an enable storage unit, and said method further comprises:

clearing said enable storage unit after firmware is loaded into a host adapter that includes said status storage element.

4. The method of claim 2 further comprising inserting a first write statement at a predetermined location in firmware to set said input storage unit in said status storage element to indicate on said output line that the first write statement has been executed.

5. The method of claim 4 further comprising inserting a second write statement to clear said input bit in said status storage element to indicate that said write statement has been executed.

6. The method of claim 4 wherein said first write statement indicates the beginning of an idle loop and said second write statement indicates the end of said idle loop.

7. The method of claim 2, wherein said step of disconnecting is performed in response to said detection of active signal on said disable line.

8. The method of claim 2, wherein the status switching circuit also has a plurality of enable lines corresponding to the plurality of input lines, and further wherein, the step of connecting said output line to said first input line is performed in response to an active signal on a first enable line corresponding to said first input line, if each enable line other than said first enable line carries an inactive signal.

9. The method of claim 8, wherein the status switching circuit also has a default input line, and the method further comprises:

connecting said output line to said default input line in response to an inactive signal on each of said enable lines.