Multi-segmented bus and method of operation

• US 5,978,880 A
• Filed: 05/23/1995
• Issued: 11/02/1999
• Est. Priority Date: 03/06/1990
• Status: Expired due to Term

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Inventors: Gastinel, Jean, Gunning, William F., Overton, Michael, Bruce, Richard H.
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): DHARIA, RUPAL
• Application Number:
  US08/447,648
• Time in Patent Office: 1,624 Days
• Field of Search: 395/281, 395/285, 395/306, 395/309, 395/310, 395/307, 395/308, 395/500, 326/30, 326/86, 371/22.3
• US Class Current: 710/316
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/409 Mechanical coupling back panels H05K7/1438

Abstract

A multi-level hierarchical bus architecture implemented with a multi-chip package and a modular shared-bus provides high bandwidth. All IC components are mounted on standardized multi-chip packages. Each multi-chip package includes bus interface chips for providing communication from the integrated circuits to a board bus. One multi-chip package contains additional bus interface circuitry for providing communication from the board bus to a backplane bus.

Claims

1. A synchronous segmented shared bus for communication in a computer comprising:

a plurality of first-level bus segments;

a plurality of multi-chip modules, each module having a first-level bus segment, each module having means for connecting a plurality of integrated circuit chips to said first-level bus segment;

a plurality of second-level bus segments, at least one of said second-level bus segments forming a connection between a first and second of said multi-chip modules;

at least one first-level bus interface chip on each said multi-chip module for storing and transferring data between one of said first-level bus segments and one of said second-level bus segments;

at least one third-level bus segment forming a connection between a first and second of said second-level bus segments; and

at least one second-level bus interface chip for storing and transferring data between one of said second-level bus segments and said third-level bus segment.

2. A synchronous segmented shared bus, as claimed in claim 1, wherein

at least a first of said first-level bus interface chips provides an output to one of said second-level buses having a first voltage and a first capacitance;

and

at least a second of said first-level bus interface chips provides an output to one of said second-level busses having a voltage and capacitance substantially identical to said first voltage and said first capacitance.

3. A synchronous segmented shared bus, as claimed in claim 1, wherein

at least a first and second of said multi-chip modules can be interchanged without substantially affecting operation of said second-level bus segment.

4. A synchronous segmented shared bus, as claimed in claim 1, further comprising:

at least a second third-level bus segment connecting a third of said second-level busses and a fourth of said second-level busses; and

at least a fourth-level bus segment connecting said first of said third-level busses and said second of said third-level busses.

5. A synchronous segmented shared bus, as claimed in claim 1, further comprising:

means for transferring data from a first of said integrated circuit chips for receipt by all of said plurality of integrated circuit chips wherein said receipt of data by said plurality of chips is substantially simultaneous.

6. A synchronous segmented shared bus, as claimed in claim 1, wherein:

said plurality of first-level bus segments have a length of less than about 15 inches.

7. A synchronous segmented shared bus, as claimed in claim 1, wherein:

said plurality of first-level bus segments are formed without terminal load resistors.

8. A synchronous segmented shared bus as claimed in claim 1 wherein:

at least one of said first-level segments includes a first unidirectional portion for providing data from one of said integrated circuits to one of said second-level bus segments and a second unidirectional portion for providing data from one of said second-level bus segments to one of said integrated circuits.

9. A synchronous segmented shared bus as claimed in claim 1, wherein:

at least one of said second-level segments includes a first unidirectional portion for providing data from one of said first-level bus segments to said third-level bus segment and a second unidirectional portion for providing data from said third-level bus segment to one of first-level bus segments.

10. A synchronous segmented shared bus for communication in a computer comprising:

a plurality of first-level bus segments;

a plurality of multi-chip modules, each module having a first-level bus segment, each module having means for connecting a plurality of integrated circuit chips to said first-level bus segment, each module having first and second opposite edges;

a plurality of second-level bus segments, at least one of said second-level bus segments forming a connection between a first and second of said multi-chip modules;

at least first and second first-level bus interface chips on each said multi-chip module for storing and transferring data between one of said first-level bus segments and one of said second-level bus segments, said first and second first-level bus interface chips positioned adjacent said first and second edges, respectively;

at least one third-level bus segment forming a connection between a first and second of said second-level bus segments; and

at least one second-level bus interface chip for storing and transferring data between one of said second-level bus segments and said third-level bus segment.

11. A synchronous segmented shared bus as claimed in claim 10, further comprising:

connector means for conductively connecting said first and second first-level bus interface chips to said second-level bus segment, said connector means having a length less than about 2 mm.

12. A method of segmented shared bus communication comprising:

providing at least a first-level, a second-level and a third-level bus segment;

providing a first-level interface chip for connecting said first-level bus segment with said second-level bus segment;

providing at least first and second-level interface chips for connecting said second-level bus segments with said third-level bus segment;

transmitting data over said first-level bus segment to said first-level interface chip and holding said data in said first-level interface chip, said transmitting and holding occurring during a first bus cycle having a first period;

receiving said data from said first-level interface chip on said second-level bus segment, transmitting said data over said second-level bus segment to said first second-level interface chip and holding said data in said first second-level interface chip, said receiving, transmitting and holding occurring during a second bus cycle having a second period substantially equal to said first period; and

receiving said data from said first second-level interface chip on said third-level bus segment, transmitting said data over said third-level bus segment and holding said data in said second second-level interface chip, said receiving, transmitting and holding occurring during a third bus cycle having a third period substantially equal to said first period.

13. A method of segmented shared bus communication, as claimed in claim 12, wherein said step of transmitting data over said first-level bus segment includes transmitting said data over a first unidirectional portion of said first-level bus, and further comprising:

transmitting data over a second unidirectional portion of said first-level bus segment from said first-level interface chip simultaneously with said transmission over said first unidirectional portion.

14. A method of segmented shared bus communication comprising:

providing a plurality of first-level bus segments, a plurality of second-level bus segments and at least a first third-level bus segment;

providing a plurality of integrated circuit chips connected to said first-level bus segments;

providing a plurality of first-level interface chips for connecting said first-level bus segments with said second-level bus segments;

providing a plurality of second-level interface chips for connecting said second-level bus segments with said third-level bus segment;

transmitting data from a first of said integrated circuits over a first first-level bus segment to a first first-level interface chip and holding said data in said first first-level interface chip;

receiving said data from said first first-level interface chip on a first second-level bus segment, transmitting said data over said first second-level bus segment to a first second-level interface chip and holding said data in said first second-level interface chip;

receiving said data from said first second-level interface chip on said third-level bus segment, transmitting said data over said third-level bus segment and holding said data in said plurality of second-level interface chips;

receiving said data from said plurality of second-level interface chips on said plurality of second-level bus segments and holding said data in said plurality of first-level interface chips; and

receiving said data from said plurality of first-level interface chips on said plurality of first-level bus segments, transmitting said data over said plurality of first-level bus segments and receiving said data substantially simultaneously in all of said plurality of said integrated circuit chips.

15. A method of segmented shared bus communication, as claimed in claim 14, wherein said step of transmitting data over said first first-level bus segment includes transmitting said data over a first unidirectional portion of said first first-level bus segment, and further comprising:

transmitting data over a second unidirectional portion of said first-level bus segment from said first-level interface chip and receiving in one of said integrated circuit chips simultaneously with said transmission over said first unidirectional portion.

16. In a synchronous segmented shared bus system having at least first, second and third bus segments, a multi-chip carrier comprising:

a substrate having first and second edges and first and second faces;

a plurality of conductive traces formed on said substrate and forming said first bus segment;

a plurality of integrated circuits positioned on said first face of said substrate and coupled to said first bus segment;

at least first and second bus interface chips for receiving data from said first bus segment, holding said data and transmitting said data to said second bus segment, said first and second bus interface chips positioned on said substrate adjacent said first and second edges.

17. A multi-chip carrier, as claimed in claim 16, wherein said second bus segment has a length of less than about 15 inches.

18. A multi-chip carrier, as claimed in claim 16, wherein said substrate lies substantially in a plane parallel to said second bus segment.

19. A multi-chip carrier, as claimed in claim 16, further comprising:

a plurality of cooling fins positioned on the second face of said substrate.

20. A multi-chip carrier, as claimed in claim 16, further comprising:

connector means for conductively connecting said first and second bus interface chips to said second bus segment, said connector means having a length less than about 2 mm.

21. A multi-chip carrier, as claimed in claim 16, wherein said first bus segment is formed without a terminal load resistor.

22. A multi-chip carrier, as claimed in claim 16 wherein:

said first bus segment includes a first unidirectional portion for providing data from one of said integrated circuits to said second bus segment and a second unidirectional portion for providing data from said second bus segment to one of said integrated circuits.

23. A multi-chip carrier, as claimed in claim 16, further comprising:

at least a third bus interface chip for receiving data from said second bus segment, holding said data and transmitting said data to said third bus segment.

24. In a synchronous segmented shared bus system having at least first, second and third bus segments, a circuit board comprising:

a board base;

a plurality of traces forming said second bus segment formed in said board base lying substantially in a plane;

at least a first multi-chip carrier mounted on said board base which includes;

a substrate having first and second edges and first and second faces;

a plurality of conductive traces formed on said substrate and forming said first bus segment;

a plurality of integrated circuits positioned on said first face of said substrate and coupled to said first bus segment;

at least first and second bus interface chips for receiving data from said first bus segment, holding said data and transmitting said data to said second bus segment, said first and second bus interface chips positioned on said substrate adjacent said first and second edges;

said second bus segment extending beneath said multi-chip carrier mounted on said board substantially between said first and second bus interface chips.

25. A circuit board, as claimed in claim 24, wherein said first multi-chip carrier provides an output to said second bus segment having a first voltage and a first capacitance and further comprising:

a second multi-chip carrier coupled to said second bus segment, said second multi-chip carrier providing an output to said second bus segment having a voltage substantially equal to said first voltage and a capacitance substantially equal to said first capacitance.