Error generation circuit for testing a digital bus

• US 5,978,934 A
• Filed: 02/07/1997
• Issued: 11/02/1999
• Est. Priority Date: 02/22/1995
• Status: Expired due to Term

• Current Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Original Assignee: Adaptec Incorporated (Steel Partners Holdings LP)
• Inventors: Gates, Stillman F.
• Primary Examiner(s): Palys, Joseph E.
• Application Number:
  US08/797,802
• Time in Patent Office: 998 Days
• Field of Search: 395/183.17, 395/183.19, 395/183.06, 395/183.07, 395/185.09, 395/182.02, 395/500, 395/568, 395/569
• US Class Current: 714/41
• CPC Class Codes: G06F 11/221 to test buses, lines or interfaces, e.g. stuck-at or open line faults
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation

Abstract

In order to test a parallel digital bus, an integrated circuit adapted for coupling to the bus has a bus error generation circuit which generates and/or simulates bus error conditions on the bus. During test, an error command is loaded into a command register of the bus error generation circuit via the bus. The bus error generation circuit then decodes the command, and either: 1) generates an error condition on the bus during a subsequent bus cycle, or 2) simulates an error condition on the bus during a subsequent bus cycle. A status configuration register in the integrated circuit and status configuration registers in other devices on the bus are then read to determine whether the integrated circuit and other devices properly detected and/or handled the generated or simulated error. By providing a bus error generation circuit in the integrated circuits coupled to a bus inside a personal computer, built-in test of the personal computer is facilitated.

Claims

1. An integrated circuit, comprising:

a plurality of bus interface terminals for coupling to a PCI bus;

means for generating a parity error condition on the PCI bus when the integrated circuit is operating as a PCI bus master; and

means for simulating receipt of a parity error condition on the PCI bus when the integrated circuit is operating as a PCI bus target, there being no actual parity error condition on the PCI bus when said receipt is simulated.

2. An integrated circuit for coupling to a PCI bus, the integrated circuit comprising:

means for simulating receipt of a parity error from a device coupled to the PCI bus, the device being incapable of generating a parity error onto the PCI bus as a test; and

means for selectively generating a parity error onto the PCI bus during an address phase or a data phase when the integrated circuit is operating as either a PCI bus master or a PCI bus target.

3. A method, comprising the steps of:

(a) on an integrated circuit of a first device, receiving signals of a bus cycle on a parallel bus, said parallel bus being coupled to said integrated circuit;

(b) on said integrated circuit, simulating receipt of a bus error condition when there is no actual bus error condition on said parallel bus and asserting a signal on said parallel bus indicative of said simulated bus error condition; and

(c) setting a bit of a status register in said integrated circuit of said first device to log said simulated bus error condition;

wherein said integrated circuit comprises a bus error generation circuit that receives a bus error command from said parallel bus, the bus error generation circuit executing the bus error command to cause the simulating receipt of a bus error condition of step (b), and the bus error generation circuit can also receive a second bus error command from said parallel bus, the bus error generation circuit being capable of executing the second bus error command to cause an actual error condition on the parallel bus.

4. A integrated circuit comprising:

a plurality of terminals coupled to a parallel bus of a personal computer;

a command register writable from said parallel bus; and

means for executing a first command stored in said command register and thereby simulating a bus error condition on said parallel bus when there is no actual bus error condition on said parallel bus, said means also being for executing a second command stored in said command register and thereby causing an actual error condition on said parallel bus of said personal computer.

5. The integrated circuit of claim 4, wherein said means is also for asserting a signal onto said parallel bus during execution of said first command, said signal being indicative of said simulated bus error condition.

6. An integrated circuit coupled to a parallel bus of a personal computer, comprising:

a first plurality of address and data terminals coupled to address and data lines of the parallel bus of the personal computer;

a parity generator having a plurality of input leads coupled to the first plurality of address and data terminals;

a second terminal coupled to a parity line of the parallel bus of the personal computer;

a third terminal coupled to a parity error response line of the parallel bus of the personal computer;

a bus error generation circuit having a first input lead coupled to an output lead of the parity generator, the bus error generation circuit having a first output lead and a second input lead coupled to the second terminal, the bus error generation circuit having a third input lead coupled to the third terminal, the bus error generation circuit also having a second plurality of output leads coupled to the plurality of input leads of the parity generator and to the first plurality of address and data terminals, the bus error generation circuit being capable of inverting a parity value received from the parity generator and outputting an inverted parity value on the second terminal; and

a register having a plurality of output leads, the plurality of output leads being coupled to a second plurality of input leads of the bus error generation circuit so that information stored in the register can pass through the bus error generation circuit and to the first plurality of address and data terminals,

wherein the bus error generation circuit comprises;

means for inverting a value received on the second terminal; and

a parity error check circuit outputting an error signal onto the third terminal if a parity determined for information received on the first plurality of address and data terminals differs from a value received from the means for inverting.