Method and apparatus for optimizing a gated clock structure using a standard optimization tool

• US 5,980,092 A
• Filed: 11/19/1996
• Issued: 11/09/1999
• Est. Priority Date: 11/19/1996
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: Engelbrecht, Kenneth L., Merryman, Kenneth E., Cleereman, Kevin C.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US08/752,620
• Time in Patent Office: 1,085 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/578, 395/551, 395/552, 395/555, 395/556, 395/558
• US Class Current: 716/108
• CPC Class Codes: G06F 2117/04 Clock gating
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

A method and apparatus for using an optimization tool to optimize a design that uses a gated clock structure. In short, the present invention allows a standard optimizer tool to determine the relative timing of two or more signals that arrive at a logic gate, wherein the logic gate forms a gated clock signal. Typically, standard optimizer tools can only check the relative timing between two or more signals that arrive at a storage element. In accordance with the present invention, selected logic gates may be modeled as a storage element. Thus, a standard optimizer tool may be used to correctly optimize a design that uses a gated clock structure, and in particular, to correctly optimize the logic that provides the clock and enable signals to a clock gating element.

Claims

1. A method for optimizing a circuit design having a logic element such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, the method comprising the steps of:

a. modeling the logic element as a storage element, wherein the storage element has a predefined setup time associated therewith; and

b. optimizing the circuit design using an optimization tool, wherein the optimization tool optimizes the circuit design such that the first signal arrives at the storage element relative to the second signal within the predefined setup time.

2. A method for optimizing a circuit design having a logic element such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, the method comprising the steps of:

a. modeling the logic element as a storage element, wherein the storage element has a predefined hold time associated therewith; and

b. optimizing the circuit design using an optimization tool, wherein the optimization tool optimizes the circuit design such that the first signal arrives at the storage element relative to the second signal within the predefined hold time.

3. A method for optimizing a circuit design having a logic element such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, the method comprising the steps of:

a. modeling the logic element as a storage element, wherein the storage element has a predefined setup and hold time associated therewith; and

b. optimizing the circuit design using an optimization tool, wherein the optimization tool optimizes the circuit design such that the first signal arrives at the storage element relative to the second signal within the predefined setup and hold times.

4. A method for optimizing a clock tree within a circuit design using an optimization tool, wherein the clock tree includes a logic element that receives a clock signal and a clock control signal, the method comprising the steps of:

a. modeling the logic element as a storage element, wherein the storage element has a predefined setup time associated therewith; and

b. optimizing the clock tree using the optimization tool, wherein the optimization tool optimizes the clock tree such that the clock control signal arrives at the storage element within the predefined setup time of the clock signal.

5. A method for optimizing a clock tree within a circuit design using an optimization tool, wherein the clock tree includes a logic element that receives a clock signal and a clock control signal, the method comprising the steps of:

a. modeling the logic element as a storage element, wherein the storage element has a predefined hold time associated therewith; and

b. optimizing the clock tree using the optimization tool, wherein the optimization tool optimizes the clock tree such that the clock control signal arrives at the storage element within the predefined hold time of the clock signal.

6. A method for optimizing a clock tree within a circuit design using an optimization tool, wherein the clock tree includes a logic element that receives a clock signal and a clock control signal, the method comprising the steps of:

a. modeling the logic element as a storage element, wherein the storage element has a predefined setup and hold time associated therewith; and

b. optimizing the clock tree using the optimization tool, wherein the optimization tool optimizes the clock tree such that the clock control signal arrives at the storage element within the predefined setup and hold times of the clock signal.

7. A method according to claim 6 wherein the storage element is a register.

8. A method according to claim 7 wherein said register has a data input and a clock input, and the clock signal is provided to the clock input and the clock control signal is provided to the data input.

9. A method for optimizing a clock tree within a circuit design using an optimization tool, wherein the clock tree includes a logic element that receives a clock signal and a clock control signal, the method comprising the steps of:

a. replacing the logic element with a storage element; and

b. optimizing the clock tree using the optimization tool, wherein the optimization tool optimizes the clock tree such that the clock control signal arrives at the storage element within a predetermined time of the clock signal.

10. A method according to claim 9 further comprising the step of:

c. replacing the storage element with the logic element after the optimization step (b).

11. A method according to claim 10 wherein said optimization step (b) does not optimize the storage element itself.

12. A method for optimizing a clock tree within a circuit design using an optimization tool, wherein the clock tree includes a logic element that receives a clock signal and a clock control signal, the clock signal providing a clock pulse wherein the clock pulse has a leading edge, a trailing edge, and a clock pulse width, the clock control signal providing a control pulse wherein the control pulse may overlap the leading edge of the clock pulse by a desired leading overlap amount and may overlap the trailing edge of the clock pulse by a desired trailing overlap amount, the method comprising the steps of:

a. modeling the logic element as a storage element; and

b. optimizing the clock tree using the optimization tool, wherein the optimization tool optimizes the clock tree such that the control pulse overlaps the leading edge of the clock pulse by the desired leading overlap amount.

13. A method for optimizing a clock tree within a circuit design using an optimization tool, wherein the clock tree includes a logic element that receives a clock signal and a clock control signal, the clock signal providing a clock pulse wherein the clock pulse has a leading edge, a trailing edge, and a clock pulse width, the clock control signal providing a control pulse wherein the control pulse may overlap the leading edge of the clock pulse by a desired leading overlap amount and may overlap the trailing edge of the clock pulse by a desired trailing overlap amount, the method comprising the steps of:

a. modeling the logic element as a storage element; and

b. optimizing the clock tree using the optimization tool, wherein the optimization tool optimizes the clock tree such that the control pulse overlaps the trailing edge of the clock pulse by the desired trailing overlap amount.

14. A method for optimizing a clock tree within a circuit design using an optimization tool, wherein the clock tree includes a logic element that receives a clock signal and a clock control signal, the clock signal providing a clock pulse wherein the clock pulse has a leading edge, a trailing edge, and a clock pulse width, the clock control signal providing a control pulse wherein the control pulse may overlap the leading edge of the clock pulse by a desired leading overlap amount and may overlap the trailing edge of the clock pulse by a desired trailing overlap amount, the method comprising the steps of:

a. modeling the logic element as a storage element; and

b. optimizing the clock tree using the optimization tool, wherein the optimization tool optimizes the clock tree such that the control pulse overlaps the leading edge of the clock pulse by the desired leading overlap amount and overlaps the trailing edge of the clock pulse by the desired trailing overlap amount.

15. Apparatus for,optimizing a circuit design having a logic element therein such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, comprising:

a. modeling means for modeling the logic element as a storage element, wherein the storage element has a predetermined setup time associated therewith; and

b. optimizing means coupled to said modeling means for optimizing the circuit design such that the first signal arrives at the storage element within the predetermined setup time of the second signal.

16. Apparatus for optimizing a circuit design having a logic element therein such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, comprising:

a. modeling means for modeling the logic element as a storage element, wherein the storage element has a predetermined hold time associated therewith; and

b. optimizing means coupled to said modeling means for optimizing the circuit design such that the first signal arrives at the storage element within the predetermined hold time of the second signal.

17. Apparatus for,optimizing a circuit design having a logic element therein such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, comprising:

a. modeling means for modeling the logic element as a storage element, wherein the storage element has a predetermined setup and hold time associated therewith; and

b. optimizing means coupled to said modeling means for optimizing the circuit design such that the first signal arrives at the storage element within the predetermined setup and hold times of the second signal.

18. Apparatus according to claim 17 wherein said logic element comprises a two-input gate.

19. Apparatus according to claim 18 wherein said modeling means comprises a timing model of a register bit having a clock and a data input, the clock input being coupled to a first one of the inputs of the two-input gate and the data input being coupled to the second one of the inputs of the two-input gate.

20. Apparatus according to claim 19 wherein said timing model defines the setup time and the hold time for the register bit.

21. Apparatus according to claim 20 wherein said optimizing means comprises an optimization tool.

22. Apparatus according to claim 21 wherein said optimization tool checks the setup time and the hold time of the register bit, thereby checking when the first signal arrives at the register bit relative to the second signal.

23. Apparatus for optimizing a circuit design having a logic element such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, the method comprising the steps of:

a. substituting means for substituting the logic element with a storage element wherein the storage element has a predetermined setup time associated therewith; and

b. optimizing means coupled to said substituting means for optimizing the circuit design such that the first signal arrives at the storage element within the predetermined setup time of the second signal.

24. Apparatus for optimizing a circuit design having a logic element such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, the method comprising the steps of:

a. substituting means for substituting the logic element with a storage element wherein the storage element has a predetermined hold time associated therewith; and

b. optimizing means coupled to said substituting means for optimizing the circuit design such that the first signal arrives at the storage element within the predetermined hold time of the second signal.

25. Apparatus for optimizing a circuit design having a logic element such that a first signal and a second signal arrive at the logic element within a predetermined time of one another, the method comprising the steps of:

a. substituting means for substituting the logic element with a storage element wherein the storage element has a predetermined setup and hold time associated therewith; and

b. optimizing means coupled to said substituting means for optimizing the circuit design such that the first signal arrives at the storage element within the predetermined setup and hold times of the second signal.

26. Apparatus according to claim 25 further comprising a re-substituting means for re-substituting the logic element for the storage element.