Integrated circuit layout routing using multiprocessing

• US 5,980,093 A
• Filed: 12/04/1996
• Issued: 11/09/1999
• Est. Priority Date: 12/04/1996
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Koford, James S., Jones, Edwin
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US08/760,641
• Time in Patent Office: 1,070 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491
• US Class Current: 716/129
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

A multithreaded wavefront routing system for simultaneously planning routes for wiring a semiconductor chip surface. The surface has a plurality of grids located thereon, and routes are planned according to a predetermined netlist. The system steps across the surface from a first location to a second location in a wave-type pattern. The system sequentially steps through the grid arrangement on the chip surface and plans routing one grid at a time using a plurality of threaded processors. The system recognizes pins as it steps through grids and determines a plan for the current grid by evaluating current wire position, target pin location, and any currently planned routes, designating reserved locations wherein the route may be planned subsequent to the current grid, and establishing a wire direction for each wire traversing the current grid. The system plans wiring through grids using multiple threaded processors employing shared memory and a semi-hard coded rule based expert system applying heuristics by planning various routes based on current and potential wire locations.

The system propagates wiring and performs memory bookkeeping functions. The system also has the capability to plan an additional route from one target pin toward a first pin. Meetings between routes are designated and resolved. Reservations may be established when a processor plans a route. Mutex locks may be utilized to avoid multiprocessor conflicts.

Claims

1. A multithreaded wavefront routing system for creating a plan of a route for wiring for a semiconductor chip surface having a grid arrangement located thereon based on a netlist, comprising:

a sequencing processor for sequentially stepping through the grid arrangement from one chip surface location to another chip surface location in a wavefront, thereby establishing a current grid on the chip surface; and

a plurality of processors, wherein each processor comprises;

a pin identifier for recognizing pins located on the surface of the chip;

a planner for establishing a proposed route proceeding from a first pin on the chip surface to a subsequent pin on the chip surface; and

a current grid wire direction planner for individually planning a direction for a wire traversing the current grid.

2. The multithreaded wavefront routing system of claim 1, further comprising a marker for marking connections between routes planned between recognized pins.

3. The multithreaded wavefront routing system of claim 1, further comprising a propagator for propagating from the current grid to a subsequent grid.

4. The multithreaded wavefront routing system of claim 1, further comprising a bookkeeper for performing memory bookkeeping functions.

5. The multithreaded wavefront routing system of claim 1, wherein said planner comprises a semi-hard coded rule based expert system which applies a group of heuristics and plans various routes according to current location of each wire and potential wire locations.

6. The multithreaded wavefront routing system of claim 1, wherein said planner further comprises a reverse direction planner for planning an additional route from one target pin toward the first pin.

7. The multithreaded wavefront routing system of claim 6, wherein the route is planned by a first processor and the additional route is planned by a second processor.

8. The multithreaded wavefront routing system of claim 7, wherein completion of said planned route and said additional planned route result in said first processor and said second processor separately designating meetings, and said meetings are resolved by a meeting resolution processor.

9. The multithreaded wavefront routing system of claim 8, wherein the meeting resolution processor is either the first or second processor.

10. The multithreaded wavefront routing system of claim 1, further comprising a locking mechanism for establishing a lock to avoid concurrent processing by the plurality of processors.

11. The multithreaded wavefront routing system of claim 10, wherein said locking mechanism employs mutex locks.

12. The multithreaded wavefront routing system of claim 1, wherein said planner comprises:

an evaluator for evaluating current wire position;

a target pin locator for assessing a target pin location;

a route appraiser for appraising currently planned routes; and

a location designator for designating reserved locations wherein the route may be planned subsequent to said current grid.

13. The multithreaded wavefront routing system of claim 12, wherein said location designator reserves a line of grids on the chip surface.

14. The multithreaded wavefront routing system of claim 12, wherein said location designator lifts reservations on any unreserved locations.

15. A method for creating a routing plan for wiring a semiconductor chip surface based on a given netlist, comprising the steps of:

establishing a first location, a second location, and a grid system on said chip; and

sequentially traversing from said first location to said second location by sequentially stepping through grids on the surface to establish a current grid using a plurality of processors, comprising the substeps of;

recognizing pin positions on said surface; and

simultaneously planning routes from a plurality of first pins through the current grid toward at least one subsequent target pin using said plurality of processors.

16. The method of claim 15, further comprising the substep of propagating to a subsequent grid after said simultaneous route planning substep.

17. The method of claim 16, wherein establishing the grid system comprises establishing a plurality of grids on the chip surface and designating a current grid.

18. The method of claim 16, further comprising the step of establishing a lock to avoid concurrent processing by the plurality of processors.

19. The method of claim 18, wherein said lock establishing step comprises using mutex locks.

20. The method of claim 16, further comprising an additional route planning substep of planning a route from one target pin toward the first pin, wherein said additional route planning substep occurs simultaneously with planning the route from the first pin toward at least one subsequent target pin.

21. The method of claim 20, wherein said route is planned by a first processor and said additional route is planned by a second processor.

22. The method of claim 21, wherein completion of said planned route and said additional planned route result in said first processor and said second processor separately designating meetings, and said meetings are resolved subsequent to designation by said processors.

23. The method of claim 16, wherein said route planning step comprises:

determining a plan for the current grid using each processor according to the substeps of;

evaluating current wire position;

assessing target location;

appraising currently planned routes;

designating reserved locations wherein the route may be planned subsequent to said current grid; and

establishing a wire direction for each wire traversing the current grid.

24. The method of claim 23, wherein said designating substep further comprises removing reservations on any determined unreserved locations.

25. The method of claim 23, wherein said appraising, designating, and establishing substeps utilize a semi-hard coded rule based expert system which applies a group of heuristics and plans various routes according to where each wire is located and potential wire locations.

26. The method of claim 23, wherein said designating substep comprises reserving locations.

27. The method of claim 26, wherein location reservation comprises reserving a line of grids.

28. The method of claim 16, further comprising the step of performing memory bookkeeping functions after said propagating step.

29. A method of simultaneously planning routes for wiring a semiconductor chip surface having a plurality of grids located thereon based on a given netlist from a plurality of first pins through a current grid toward at least one subsequent target pin using a plurality of processors, comprising the steps of:

determining a plan for the current grid using each processor according to the substeps of;

evaluating current wire position;

assessing target location;

appraising currently planned routes;

designating reserved locations wherein the route may be planned subsequent to said current grid; and

establishing a wire direction for each wire traversing the current grid.

30. The method of claim 29, further comprising the substep of planning an additional route from one target pin toward the first pin, wherein said additional route planning occurs simultaneously with planning the route from the first pin toward at least one subsequent target pin.

31. The method of claim 30, wherein said route is planned by a first processor and said additional route is planned by a second processor.

32. The method of claim 31, wherein completion of said planned route and said additional planned route result in said first processor and said second processor separately designating meetings, and said meetings are resolved subsequent to designation by said processors.

33. The method of claim 29, wherein said designating substep comprises reserving locations.

34. The method of claim 33, wherein said designating substep further comprises removing reservations on determined unreserved locations.

35. The method of claim 33, wherein location reservation comprises reserving a line of grids.

36. The method of claim 29, further comprising the step of establishing a lock to avoid concurrent processing by the plurality of processors.

37. The method of claim 36, wherein said lock establishing step comprises using mutex locks.

38. The method of claim 29, wherein said appraising, designating, and establishing substeps utilize a semi-hard coded rule based expert system which applies a group of heuristics and plans various routes according to where each wire is located and potential wire locations.

39. A method of planning multiple routes along a surface of a semiconductor chip surface divided into a plurality of grids using multiple processing threads according to a predetermined netlist, comprising the following steps:

sequentially stepping through the grid arrangement from one chip surface location to another chip surface location in a wavefront, thereby establishing a current grid on the chip surface;

recognizing pins along the wavefront;

using each processing thread to separately plan routes between pins according to the netlist; and

individually planning a direction for each wire traversing the current grid.

40. The method of claim 39, further comprising propagating from the current grid to a subsequent grid after said individual planning step.

41. The method of claim 40, further comprising the step of performing memory bookkeeping functions after said propagating step.

42. The method of claim 40, wherein said using step comprises:

evaluating current wire position;

assessing a target pin location;

appraising currently planned routes; and

designating reserved locations wherein the route may be planned subsequent to said current grid.

43. The method of claim 42, wherein said designating substep comprises reserving locations.

44. The method of claim 43, wherein said designating substep further comprises lifting reservations on any unreserved locations.

45. The method of claim 42, wherein said appraising, designating, and establishing substeps utilize a semi-hard coded rule based expert system which applies a group of heuristics and plans various routes according to where each wire is located and potential wire locations.

46. The method of claim 39, further comprising the step of establishing a lock to avoid concurrent processing by the multiple processing threads.

47. The method of claim 46, wherein locations are locked using mutex locks.

48. The method of claim 39, further comprising the substep of planning an additional route from one target pin toward the first pin, wherein said additional route planning occurs simultaneously with planning the route from the first pin toward at least one subsequent target pin.

49. The method of claim 48, wherein said route is planned by a first processor and said additional route is planned by a second processor.

50. The method of claim 49, wherein location reservation comprises reserving a line of grids.

51. The method of claim 49, wherein completion of said planned route and said additional planned route result in said first processor and said second processor separately designating meetings, and said meetings are resolved subsequent to designation by said processors.