Integrated multi-layer test pads and methods therefor

• US 5,981,302 A
• Filed: 02/23/1999
• Issued: 11/09/1999
• Est. Priority Date: 05/21/1997
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG
• Original Assignee: International Business Machines Corporation, Siemens AG
• Inventors: Davies, William, Hoyer, Ronald, Prein, Frank, Mendelson, Ron, Alswede, Frank
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Chambliss, Alonzo
• Application Number:
  US09/256,048
• Time in Patent Office: 259 Days
• Field of Search: 257/48, 257/203, 257/211, 257/758, 324/757, 324/765, 324/766, 29/593, 438/6, 438/15, 438/17, 438/18, 438/612, 438/123, 438/614
• US Class Current: 438/15
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: Y10S 257/923 with means to optimize electrical conductor current carrying capacity, e.g. particular conductor aspect ratio

Abstract

A multi-layer test pad on a semiconductor wafer, which includes an underlying matrix of interconnected first pads, which are arranged in rows and columns. The multi-layer test pad includes an oxide layer disposed above the underlying matrix and in between the rows and columns. The multi-layer test pad further includes an overlying matrix of interconnected second pads disposed above the oxide layer. Each of the second pads completely overlaps at least nine of the first pads, including four oxide regions surrounding a center first pad of the nine of the first pads. The nine of the first pads are arranged as 3×3 block of the first pads.

Claims

1. A method for forming an integrated multi-layer test pad on a semiconductor wafer, comprising:

forming an underlying matrix of interconnected first pads, said first pads being configured for electrically coupling to said integrated semiconductor device;

depositing an oxide layer above said underlying matrix; and

forming an overlying matrix of interconnected second pads above said oxide layer, said overlying matrix being electrically coupled to said underlying matrix by at least one conductive via through said oxide layer, one of said first pads having a first surface area smaller than a second surface area of one of said second pads, said one of said second pads being disposed above and completely overlapping said one of said first pads, whereby said one of said second pads masks an area under said one of said second pads, including said one of said first pads, from being etched by an oxide etchant.

2. The method of claim 1 wherein said forming said underlying matrix of interconnected first pads comprises:

depositing a first conductive layer comprising tungsten;

etching said first conductive layer, thereby creating said underlying matrix.

3. The method of claim 2 wherein said forming said overlying matrix of interconnected second pads comprises:

depositing a second conductive layer comprising aluminum above said oxide layer; and

etching said second conductive layer, thereby creating said overlying matrix.

4. The method of claim 1 wherein said overlying matrix of interconnected second pads comprises a plurality of periphery second pads and at least one center second pad, a surface area of said center second pad being at least larger than an area occupied by a 3×

3 block of said first pads, said 3×

3 block of said first pads being disposed below said center second pad.

5. The method of claim 4 wherein each of said periphery second pads is larger in surface area than said center second pad.

6. The method of claim 5 further comprising four corner second pads disposed at four corners of said multi-layer test pad, each of said four corner second pads being larger than said center second pad.

7. The method of claim 1 wherein said overlying matrix of interconnected second pads comprises a plurality of periphery second pads and at least one center second pad, a surface area of said center second pad being substantially equal to an area occupied by a 3×

3 block of said first pads, said 3×

3 block of said first pads being disposed below said center second pad.

8. The method of claim 1 further comprising:

forming an intermediate metallization layer, said intermediate metallization layer being disposed in between said underlying matrix and said overlying matrix, said intermediate metallization layer being coupled to both said overlying matrix and said underlying matrix.