Near chip size integrated circuit package

• US 5,981,314 A
• Filed: 10/31/1996
• Issued: 11/09/1999
• Est. Priority Date: 10/31/1996
• Status: Expired due to Term

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Glenn, Thomas P., Hollaway, Roy D., Panczak, Anthony E.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Chambliss, Alonzo
• Application Number:
  US08/741,797
• Time in Patent Office: 1,104 Days
• Field of Search: 438/110, 438/113, 438/114, 438/125, 438/126, 438/462, 438/464, 438/458, 438/112, 438/123, 438/124, 438/127, 438/613, 257/691, 257/693, 257/700, 257/784, 257/787, 361/760
• US Class Current: 438/127
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15173 : in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15183 : in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A plurality of integrated circuit chip (IC chip) packages are fabricated simultaneously from a single insulating substrate having sections. In each section, an IC chip is attached. Bonding pads on the IC chip are electrically connected to first metallizations on a substrate first surface. The first metallizations, IC chip including bonding pads and first substrate surface are then encapsulated. Interconnection balls or pads are formed at substrate bonding locations on a substrate second surface, the interconnection pads or balls being electrically connected to corresponding first metallizations. The substrate and encapsulant are then cut along the periphery of each section to form the plurality of IC chip packages.

Claims

1. A method of forming a plurality of integrated circuit chip packages from an insulating substrate, said method comprising the steps of:

providing said insulating substrate which has sections, said sections having first metallizations formed on a first surface of said insulating substrate;

mounting an integrated circuit chip in each of said sections, said integrated circuit chips having first surfaces with bonding pads formed thereon;

electrically connecting said bonding pads to corresponding ones of said first metallizations with bond wires;

forming a dam on said first surface of said insulating substrate around a perimeter of said insulating substrate;

encapsulating said bonding pads, said first surfaces of said integrated circuit chips, said first metallizations and said first surface of said insulating substrate with a layer of encapsulant by filling a pocket defined by said dam with an electrically insulating encapsulant; and

cutting said layer of encapsulant and said insulating substrate along a periphery of each of said sections to form said plurality of integrated circuit chip packages.

2. The method of claim 1 wherein said sections have second metallizations formed on a second surface of said insulating substrate, wherein said sections have conductive through-holes extending from said first surface of said insulating substrate to said second surface of said insulating substrate and wherein said conductive through-holes are electrically connected to corresponding ones of said first metallizations and to corresponding ones of said second metallizations.

3. The method of claim 2 wherein said second metallizations are connected on first ends to said corresponding conductive through-holes, said method further comprising the step of forming interconnection balls at second ends of said second metallizations.

4. The method of claim 2 wherein said second metallizations are connected on first ends to said corresponding conductive through-holes, said method further comprising the step of forming interconnection pads at second ends of said second metallizations.

5. The method of claim 3 wherein said step of mounting further comprises mounting second surfaces of said integrated circuit chips, opposite said first surfaces of said integrated circuit chips, to said first surface of said insulating substrate with adhesive.

6. The method of claim 3 further comprising the step of forming interconnection balls at substrate bonding locations on a second surface of said insulating substrate, opposite said first surface of said insulating substrate, wherein said interconnection balls are electrically connected to corresponding ones of said first metallizations.

7. The method of claim 1 further comprising the step of forming interconnection pads at substrate bonding locations on a second surface of said insulating substrate, opposite said first surface of said insulating substrate, wherein said interconnection pads are electrically connected to corresponding ones of said first metallizations.

8. The method of claim 1 further comprising the step of embedding a heat slug into said layer of encapsulant over each of said sections such that each of said heat slugs is contained within said layer of encapsulant.

9. A method of packaging an integrated circuit chip having a first surface with bonding pads formed thereon, said method comprising the steps of:

mounting a second surface of said integrated circuit chip to a first surface of an insulating substrate having sections, said integrated circuit chip being mounted to said insulating substrate in one of said sections;

electrically connecting each of said bonding pads to corresponding first metallizations formed on said first surface of said insulating substrate with bond wires;

forming a dam on said first surface of said insulating substrate around a perimeter of said insulating substrate;

encapsulating said bonding pads, said first surface of said integrated circuit chip, said bond wires and said first surface of said insulating substrate in a layer of encapsulant by filling a pocket defined by said dam with an electrically insulating encapsulant;

forming interconnection balls at bonding locations on a second surface of said insulating substrate, wherein each of said interconnection balls is electrically connected to a corresponding one of said first metallizations; and

cutting said insulating substrate and said layer of encapsulant along a periphery of said one section in which said integrated circuit is mounted.

10. A method of forming a plurality of integrated circuit chip packages from an insulating substrate, said method comprising the steps of:

providing said insulating substrate which has sections, said sections having first metallizations formed on a first surface of said insulating substrate;

placing a first surface of an integrated circuit chip adjacent said first surface of said insulating substrate in each of said sections, said first surfaces of said integrated circuit chips having bonding pads formed thereon;

forming flip chip connections between said bonding pads and corresponding ones of said first metallizations;

applying an underfill material between said integrated circuit chips and said substrate to encapsulate said flip chip connections;

forming a dam on said first surface of said insulating substrate around a perimeter of said insulating substrate;

encapsulating a second surface of said integrated circuit chips and said first surface of said insulating substrate with a layer of encapsulant by filling a pocket defined by said dam with an encapsulant; and

cutting said layer of encapsulant and said insulating substrate along a periphery of each of said sections to form said plurality of integrated circuit chip packages.