Methods of forming integrated circuits having memory cell arrays and peripheral circuits therein

• US 5,981,324 A
• Filed: 10/23/1997
• Issued: 11/09/1999
• Est. Priority Date: 10/23/1996
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Won-shik, Kim, Young-pil, Kang, Myeon-koo, Seo, Young-woo
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US08/956,584
• Time in Patent Office: 747 Days
• Field of Search: 438/200, 438/210, 438/230, 438/231, 438/232, 438/250, 438/251, 438/649, 438/683
• US Class Current: 438/210
• CPC Class Codes: H10B 12/01 Manufacture or treatment
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

Methods of forming integrated circuits having memory cell arrays therein and peripheral circuits therein include the steps of selectively forming more lightly doped source and drain regions for transistors in the memory cell arrays. These more lightly doped source and drain regions are designed to have fewer crystalline defects therein caused by ion implantation, so that storage capacitors coupled thereto have improved refresh characteristics. Preferred methods include the steps of forming a first well region of first conductivity type (e.g., P-type) in a memory cell portion of a semiconductor substrate and a second well region of first conductivity type in a peripheral circuit portion of the semiconductor substrate extending adjacent the memory cell portion. First and second insulated gate electrodes are then formed on the first and second well regions, respectively, using conventional techniques. First dopants of second conductivity type are then implanted at a first dose level into the first and second well regions, using the first and second insulated gate electrodes as an implant mask. These dopants are then diffused to form lightly doped source and drain regions adjacent the first and second insulated gate electrodes. Second dopants of second conductivity type are then selectively implanted at a second dose level, greater than the first dose level, into the second well region using self-alignment techniques. However, these dopants are preferably not implanted into the first well region. These second dopants are then diffused into the second source/drain regions.

Claims

1. A method of forming an integrated circuit memory device, comprising the steps of:

forming a first conductivity type well region in a memory cell array portion of a semiconductor substrate;

forming first and second conductivity type well regions at spaced locations in a peripheral circuit portion of the semiconductor substrate, adjacent the memory cell array portion of the semiconductor substrate;

forming a first insulated gate electrode on the first conductivity type well region in the memory cell array portion of the semiconductor substrate;

forming second and third insulated gate electrodes on the first and second conductivity type well regions in the peripheral circuit portion of the semiconductor substrate, respectively;

selectively implanting dopants of second conductivity type at a first dose level into first conductivity type well region in the memory cell array portion of the semiconductor substrate, using the first insulated gate electrode as an implant mask, and implanting dopants of second conductivity type at the first dose level into the first conductivity type well region in the peripheral circuit portion of the semiconductor substrate, using the second insulated gate electrode as an implant mask;

selectively implanting dopants of first conductivity type at a second dose level into the second conductivity type well region in the peripheral circuit portion of the semiconductor substrate, using the third insulated gate electrode as an implant mask;

forming sidewall spacers on the second and third insulated gate electrodes;

selectively implanting dopants of second conductivity type at a third dose level, greater than the first dose level, into the first conductivity type well region in the peripheral circuit portion of the semiconductor substrate, using the second insulated gate electrode and respective sidewall spacers as an implant mask, but not into the first conductivity type well region in the memory cell array portion of the semiconductor substrate; and

selectively implanting dopants of first conductivity type at a fourth dose level, greater than the second dose level, into the second conductivity type well region in the peripheral circuit portion of the semiconductor substrate, using the third insulated gate electrode and respective sidewall spacers as an implant mask.

2. The method of claim 1, further comprising the step of forming a metal silicide layer on the first, second and third insulated gate electrodes.

3. The method of claim 2, wherein the first, second and third insulated gate electrodes contain first, second and third polycrystalline silicon gates;

and wherein said step of forming a metal silicide layer on the first, second and third insulated gate electrodes comprises forming a layer of refractory metal on the first, second and third polycrystalline silicon gates and then annealing the layer of refractory metal to form a metal silicide layer.

4. The method of claim 3, further comprising the step of exposing the annealed layer of refractory metal to a solution containing ammonium hydroxide.

5. The method of claim 3, wherein said step of forming sidewall spacers comprises depositing an insulating layer on the first, second and third insulated gate electrodes and then anisotropically etching the deposited insulating layer.

6. The method of claim 3, wherein said step of selectively implanting dopants of second conductivity type at a first dose level comprises implanting dopants of second conductivity type to form lightly doped source and drain regions having a second conductivity type doping concentration therein in a range between 1×

10¹⁷ cm^-3 and 1×

10¹⁸ cm^-3 ; and

wherein said step of forming a metal silicide layer comprises forming a metal silicide layer on and in electrical contact with the lightly doped source and drain regions.

7. The method of claim 6, further comprising the step of forming a storage capacitor electrode electrically coupled to one of the lightly doped source and drain regions.

8. A method of forming an integrated circuit memory device, comprising the steps of:

forming a first well region of first conductivity type in a memory cell portion of a semiconductor substrate;

forming a second well region of first conductivity type well region in a peripheral circuit portion of the semiconductor substrate extending adjacent the memory cell portion;

forming first and second insulated gate electrodes on the first and second well regions, respectively;

implanting first dopants of second conductivity type at a first dose level into the first and second well regions, using the first and second insulated gate electrodes as an implant mask;

diffusing the first dopants to form first and second source/drain regions adjacent the first and second insulated gate electrodes, respectively;

forming spacers on sidewalls of the first and second insulated gate electrodes;

selectively implanting second dopants of second conductivity type at a second dose level, greater than the first dose level, into the second well region, but not into the first well region, using the second insulated gate electrode and spacers thereon as an implant mask;

diffusing the second dopants into the second source/drain regions;

forming a layer of refractory metal on the first and second insulated gate electrodes and on the first and second source/drain regions having different doping concentrations therein; and

converting the layer of refractory metal to a layer of refractory metal silicide.

9. The method of claim 8, wherein said step of diffusing the first dopants comprises diffusing the first dopants to form first and second source/drain regions having a first conductivity type doping concentration therein in a range between 1×

10¹⁷ cm^-3 and 1×

10¹⁸ cm^-3.

10. The method of claim 9, wherein said step of diffusing the second dopants comprises diffusing the second dopants into the second source/drain regions to increase the first conductivity type doping concentration therein to a level in a range between 1×

10¹⁹ cm^-3 and 1×

10²¹ cm^-3.

11. The method of claim 10, wherein said step of forming spacers comprises forming electrically insulating spacers of a material selected from the group consisting of silicon dioxide and silicon nitride.

12. The method of claim 10, wherein the first and second insulated gate electrodes comprise respective gate oxide layers having thicknesses in a range between about 80 Å

and 200 Å

.

13. The method of claim 10, wherein said converting step is followed by the step of exposing the layer of refractory metal silicide to a solution containing ammonium hydroxide.

14. The method of claim 10, further comprising the step of forming a storage capacitor electrode electrically coupled to one of the first source/drain regions.