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Method of making stacked gate memory cell structure

  • US 5,981,335 A
  • Filed: 11/20/1997
  • Issued: 11/09/1999
  • Est. Priority Date: 11/20/1997
  • Status: Expired due to Term
First Claim
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1. A method to fabricate a stacked gate memory cell comprising the steps of:

  • a) implanting a deep diffusion well of a first conductivity type in the semiconductor substrate and connecting said deep diffusion well to a deep diffusion voltage generator;

    b) implanting a second diffusion well of a second conductivity type in the deep diffusion well;

    c) forming a MOS transistor by the steps of;

    implanting a drain diffusion of the first conductivity type in the second diffusion well and connecting said drain diffusion to a bit line voltage generator,implanting a source diffusion of the second conductivity type in the second diffusion well at a channel length from the drain diffusion, strapped to said second diffusion well, and coupling said source diffusion to a source control voltage generator;

    depositing a tunnel oxide on a top surface of said semiconductor substrate in a channel area, whereby the channel length is a length dimension of the channel area, that is between said drain diffusion and said source diffusion, anddepositing a gate electrode of a first polysilicon material on the tunnel oxide above the channel area;

    d) depositing an insulating layer on the surface of said semiconductor substrate with a plurality of openings to allow connections to said second diffusion well, said source diffusion, said drain diffusion, and said gate electrode; and

    e) forming a stacked capacitor by the steps of;

    depositing a first plate of a second polysilicon material upon said insulating layer and connecting said first plate by a shorting plug to said gate electrode through one of the plurality of openings in said insulating layer, whereby said gate electrode and said first plate will form a floating gate for said MOS transistor,depositing a capacitor dielectric placed upon said first plate, anddepositing a second plate of a third polysilicon material on said capacitor dielectric and coupling said second plate to a word line voltage generator, whereby said second plate will form a control gate for said MOS transistor.

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