Vertical trench misfet and method of manufacturing the same

• US 5,981,996 A
• Filed: 02/15/1996
• Issued: 11/09/1999
• Est. Priority Date: 02/17/1995
• Status: Expired due to Term

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Fujishima, Naoto
• Primary Examiner(s): Prenty, Mark V.
• Application Number:
  US08/602,150
• Time in Patent Office: 1,363 Days
• Field of Search: 257/335, 257/339, 257/341, 257/329, 257/330
• US Class Current: 257/335
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A vertical trench MISFET is provided that includes a semiconductor substrate having a first conductivity type semiconductor, and a second conductivity type impurity layer provided on the first conductivity type semiconductor. A trench extends from a surface of the semiconductor substrate to reach said first conductivity type semiconductor. A second conductivity type base region is formed in a top portion of the semiconductor substrate, and a first conductivity type source region is formed in a part of a surface layer of the second conductivity type base region. A first conductivity type drain drift region having a small thickness is formed in a surface layer of a side wall of the trench. The drain drift region has a higher impurity concentration than a level at which a breakdown voltage measured in a hypothetical diffusion type junction is substantially equal to an element withstand voltage. A gate electrode is formed on an exposed surface of the second conductivity type base region, through a gate insulating film. A source electrode is disposed in contact with surfaces of both of the first conductivity type source region and the second conductivity type base region, while a drain electrode is disposed in contact with a rear surface of the first conductivity type semiconductor.

Claims

1. A vertical trench MISFET comprising:

a semiconductor substrate having a first conductivity type semiconductor, and a second conductivity type impurity layer disposed on the first conductivity type semiconductor;

a trench extending from a surface of said semiconductor substrate to reach said first conductivity type semiconductor;

a second conductivity type base region formed in a top portion of said semiconductor substrate;

a first conductivity type source region formed in a part of a surface layer of said second conductivity type base region;

a first conductivity type drain drift region formed in a surface layer of a side wall of said trench, said first conductivity type drain drift region having a small thickness and first impurity concentration that is higher than a second impurity concentration at which a breakdown voltage measured in a hypothetical diffusion type junction is substantially equal to an element withstand voltage;

a gate electrode formed on an exposed surface of said second conductivity type base region;

a gate insulating film provided between said gate electrode and said second conductivity type base region;

a source electrode disposed in contact with surfaces of both of said first conductivity type source region and said second conductivity type base region; and

a drain electrode disposed in contact with a rear surface of said first conductivity type semiconductor.

2. A vertical trench MOSFET as defined in claim 1, wherein said first conductivity type drain drift region consists of an impurity diffused layer.

3. A vertical trench MISFET comprising:

a first conductivity type semiconductor;

a second conductivity type impurity layer formed on a surface of said first conductivity type semiconductor;

a second conductivity type base layer formed on said second conductivity type impurity layer and having a higher impurity concentration than the second conductivity type impurity layer;

a first conductivity type source region formed in a part of a surface layer of said second conductivity type base layer;

a trench extending from a surface of said first conductivity type source region to reach said first conductivity type semiconductor;

a first conductivity type drain drift region formed in a surface layer of said second conductivity type impurity layer which is exposed to an inner surface of said trench, said first conductivity type drain drift region having a first impurity concentration that is higher than a second impurity concentration at which a breakdown voltage measured in a hypothetical diffusion type junction is substantially equal to an element withstand voltage;

a gate electrode disposed in said trench such that the gate electrode faces a surface of said second conductivity type base layer which is exposed to the inner surface of the trench, a portion of said trench other than said gate electrode being filled with an oxide film;

a gate insulating film provided between said gate electrode and said second conductivity type base layer;

a source electrode disposed in contact with both of a surface of said first conductivity type source region and an exposed surface portion of said second conductivity type base region; and

a drain electrode disposed in contact with a rear surface of said first conductivity type semiconductor.

4. A vertical trench MISFET comprising:

a first conductivity type semiconductor substrate;

a second conductivity type impurity layer formed on a surface of said first conductivity type semiconductor substrate;

a trench extending from a surface of said second conductivity type impurity layer to reach said first conductivity type semiconductor substrate;

a first conductivity type side wall region formed in a surface layer of said second conductivity type impurity layer which is exposed to an inner surface of said trench, said first conductivity type side wall region having a first impurity concentration that is higher than a second impurity concentration at which a breakdown voltage measured in a hypothetical diffusion type junction is substantially equal to an element withstand voltage;

a second conductivity type base region formed in a surface layer of said second conductivity type impurity layer and a part of a surface layer of said first conductivity type side wall region;

a first conductivity type source region formed in a part of a surface layer of said second conductivity type base region;

a gate electrode formed on a surface of said second conductivity type base region which is interposed between said first conductivity type source region and said first conductivity type side wall region;

a gate insulating film provided between said gate electrode and said second conductivity type base region;

a source electrode disposed in contact with both of a surface of said first conductivity type source region and an exposed surface portion of said second conductivity type base region;

a drain electrode disposed in contact with a rear surface of said first conductivity type semiconductor substrate; and

an oxide film filling said trench.

5. A vertical trench MISFET comprising:

a first conductivity type semiconductor substrate;

a second conductivity type impurity layer formed on a surface of said first conductivity type semiconductor substrate;

a first conductivity type impurity layer formed on said second conductivity type impurity layer;

a second conductivity type base region formed in a part of a surface layer of said first conductivity type impurity layer;

a first conductivity type source region formed in a part of a surface layer of said second conductivity type base region;

a trench extending from a surface of said first conductivity type source region to reach said first conductivity type semiconductor substrate;

a first conductivity type side wall region formed in a surface layer of said second conductivity type impurity layer which is exposed to an inner surface of said trench, said first conductivity type side wall region having a first impurity concentration that is higher than a second impurity concentration at which a breakdown voltage measured in a hypothetical diffusion type junction is substantially equal to an element withstand voltage;

a gate electrode formed on a surface of said second conductivity type base region which is interposed between said first conductivity type source region and said first conductivity type impurity layer;

a gate insulating film provided between said gate electrode and said second conductivity type base region;

a source electrode disposed in contact with surfaces of both of said second conductivity type base region and said first conductivity type source region, which surfaces are exposed to an inner surface of said trench;

an oxide film filling a portion of said trench other than said source electrode; and

a drain electrode disposed in contact with a rear surface of said first conductivity type semiconductor substrate.

6. A vertical trench MISFET comprising:

a semiconductor substrate having a first conductivity type semiconductor, and a first conductivity type impurity layer provided on the first conductivity type semiconductor, said first conductivity type impurity layer having a first impurity concentration that is higher than a second impurity concentration at which a breakdown voltage measured in a hypothetical diffusion type junction is substantially equal to an element withstand voltage;

a trench extending from a surface of said semiconductor substrate to reach said first conductivity type semiconductor;

a second conductivity type base region formed in a top portion of said semiconductor substrate;

a first conductivity type source region formed in a part of a surface layer of said second conductivity type base region;

a second conductivity type side wall region formed in a surface layer of a side wall of said trench;

a gate electrode formed on an exposed surface of said second conductivity type base region;

a gate insulating film provided between said gate electrode and said second conductivity type base region;

a source electrode disposed in contact with surfaces of both of said first conductivity type source region and said second conductivity type base region; and

a drain electrode disposed in contact with a rear surface of said first conductivity type semiconductor.

7. A vertical trench MOSFET as defined in claim 6, wherein said second conductivity type side wall region consists of an impurity diffused layer.

8. A vertical trench MISFET comprising;

a first conductivity type semiconductor;

a first conductivity type drain drift layer formed on a surface of said first conductivity type semiconductor, said first conductivity type drain drift layer having a first impurity concentration that is higher than a second impurity concentration at which a breakdown voltage measured in a hypothetical diffusion type junction is substantially equal to an element withstand voltage;

a second conductivity type base layer formed on said first conductivity type drain drift layer;

a first conductivity type source region formed in a part of a surface layer of said second conductivity type base layer;

a trench extending from a surface of said first conductivity type source region to reach said first conductivity type semiconductor;

a second conductivity type side wall region formed in a surface layer of a lower portion of said first conductivity type drain drift layer which is exposed to an inner surface of said trench, wherein said side wall region extends along a side of said trench to the first conductivity type semiconductor;

a gate electrode disposed in said trench such that the gate electrode faces a surface of an upper portion of said first conductivity type drain drift layer which is exposed to the inner surface of said trench, and a surface of said second conductivity type base layer which is exposed to the inner surface of the trench;

a gate insulating film provided between said gate electrode, and said first conductivity type drain drift layer and said second conductivity type base layer;

an oxide film filling a portion of said trench other than said gate electrode;

a source electrode disposed in contact with both of a surface of said first conductivity source region, and an exposed surface portion of said second conductivity type base layer; and

a drain electrode disposed in contact with a rear surface of said first conductivity type semiconductor.

9. A vertical trench MISFET comprising:

a first conductivity type semiconductor;

a first conductivity type impurity layer formed on said first conductivity type semiconductor, said first conductivity type impurity layer having a first impurity concentration that is higher than a second impurity concentration at which a breakdown voltage measured in a hypothetical diffusion type junction is substantially equal to an element withstand voltage;

a second conductivity type base region formed in a part of a surface layer of said first conductivity type impurity layer;

a first conductivity type source region formed in a part of a surface layer of said second conductivity type base region;

a trench extending from a surface of said first conductivity type impurity layer to reach said first conductivity type semiconductor;

a second conductivity type side wall region formed in an exposed surface layer of said first conductivity type impurity layer which is exposed to an inner surface of said trench;

a gate electrode formed on a surface of said second conductivity type base region which is interposed between said first conductivity type source region and said first conductivity type impurity layer;

a gate insulating film provided between said gate electrode and said second conductivity type base region;

a source electrode disposed in contact with both of a surface of said first conductivity type source region, and an exposed surface portion of said second conductivity type base region;

a drain electrode disposed in contact with a rear surface of said first conductivity type semiconductor; and

an oxide film filling said trench.

10. A vertical trench MISFET comprising:

a first conductivity type semiconductor;

a first conductivity type impurity layer formed on a surface of said first conductivity type semiconductor, said first conductivity type impurity layer having a first impurity concentration that is higher than a second impurity concentration at which a breakdown voltage measured in a hypothetical diffusion type junction is substantially equal to an element withstand voltage;

a second conductivity type base region formed in a part of a surface layer of said first conductivity type impurity layer;

a first conductivity type source region formed in a part of a surface layer of said second conductivity type base region;

a trench extending from a surface of said first conductivity type source region to reach said first conductivity type semiconductor;

a second conductivity type side wall region formed in a surface layer of said first conductivity type impurity layer which is exposed to an inner surface of said trench;

a gate electrode formed on a surface of said second conductivity type base region interposed between said first conductivity type source region and said first conductivity type impurity layer;

a gate insulating film provided between said gate electrode and said second conductivity type base region;

a source electrode disposed in contact with both surfaces of said second conductivity type base region and said first conductivity type source region, which surfaces are exposed to the inner surface of said trench;

an oxide film filling a portion of said trench other than said source electrode; and

a drain electrode disposed in contact with a rear surface of said first conductivity type semiconductor.