Power trench DMOS with large active cell density

• US 5,981,999 A
• Filed: 01/07/1999
• Issued: 11/09/1999
• Est. Priority Date: 01/07/1999
• Status: Expired due to Term

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Liu, Chung-Min, Tsai, Ming-Jinn, Hung, Chien-Chung, Kao, Ming-Jer, Yao, June-Min
• Primary Examiner(s): Monin, Jr., Donald L.
• Application Number:
  US09/226,278
• Time in Patent Office: 306 Days
• Field of Search: 257/341, 257/339, 257/331, 257/330, 257/141, 257/335, 257/336, 257/334, 257/328
• US Class Current: 257/339
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A design for a trench DMOS transistor having improved current carrying capability is presented. The principal improvement lies in the periodic replacement of the individual cells in the array with a protection cell of a different size. When this is done it becomes possible to significantly increase the density of cells per unit area. This results in a corresponding improvement in the amount of channel area available to the device and hence an increase in its current carrying capability.

Claims

1. A high power solid-state device, comprising:

a two-dimensional array of active DMOS cells each of which further comprises an N+ drain layer, and a first P type body which includes a first active region;

a protection cell that replaces a quantity of active cells and that further comprises a second P type body;

said first P type body being separated from the drain layer by a first distance that is no more than about 6 microns; and

said second P type body being separated from the drain layer by a second distance that is less than said first distance.

2. The solid-state device of claim 1 wherein the active DMOS cells have a density that is greater than about 20 million cells per square inch.

3. The solid-state device of claim 1 wherein the quantity of active cells replaced by the active cell is between 1 and 16.

4. The solid-state device of claim 1 wherein all cells are separated by a trench that is lined with gate insulation and filled with polysilicon.

5. The solid-state device of claim 1 having a maximum operating voltage that is between about 10 and 40 volts.

6. The solid-state device of claim 1 wherein said second distance is less than about 6 microns.

7. The solid-state device of claim 1 wherein the active DMOS cells have a rectangular or a hexagonal shape.

8. The solid-state device of claim 1 wherein said protection cell contains a second active region.

9. A high power solid-state device, comprising:

an array of active DMOS cells each of which further comprises an N+ drain layer, and a first P type body which includes a first active region;

said first P type body being separated from the drain layer by a first distance that is no more than about 4 microns;

a protection cell that replaces an active cell in the array and that further comprises a second P type body; and

said second P type body being separated from the drain layer by a second distance that is less than said first distance.

10. The solid-state device of claim 9 wherein the protection DMOS cells have a linear density of between about 1/2 and 1/16 cell pairs per active cell.

11. The solid-state device of claim 9 wherein all cells are separated by a trench that is lined with gate insulation and filled with polysilicon.

12. The solid-state device of claim 9 having a maximum operating voltage that is between about 10 and 40 volts.

13. The solid-state device of claim 9 wherein said second distance is less than about 6 microns.

14. The solid-state device of claim 9 wherein said protection cell contains a second active region.