PLL system clock generator with instantaneous clock frequency shifting

• US 5,982,210 A
• Filed: 09/02/1994
• Issued: 11/09/1999
• Est. Priority Date: 09/02/1994
• Status: Expired due to Term

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Rogers, Alan C.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): ADOLPHE, EUNJA
• Application Number:
  US08/300,028
• Time in Patent Office: 1,894 Days
• Field of Search: 327/144, 327/146, 327/147, 327/156, 327/233, 327/243, 327/244, 327/295, 327/297, 327/117, 331/17, 331/25, 375/120, 377/47, 377/48
• US Class Current: 327/156
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H03L 7/199 with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation

Abstract

The present invention provides a phase locked loop (PLL) clock generator for a digital system. The PLL clock generator is capable of an instantaneous transition between a high frequency and a low frequency, corresponding to an active mode and a slow mode, and vice versa The PLL clock generator includes a phase locking circuit, a frequency changer coupled to the output of the phase locking circuit, and a frequency controller coupled to the frequency changer. The frequency changer is capable of instantaneously changing the frequency of a first clock signal received from the phase locking circuit. The frequency controller is responsible for controlling the frequency at the output of the frequency changer. The frequency controller is responsive to a control signal which is used to transition the PLL clock generator from an active mode to a slow mode and vice versa In one embodiment, the phase locking circuit generates the first clock signal in response to a reference clock signal and a feedback clock signal. The frequency changer includes a first divider for generating a global clock signal in response to the first clock signal, and a second divider for generating a peripheral clock signal and a feedback signal in response to the global clock signal The frequency controller, responsive to the control signal is used to change the divisors of the first and second dividers simultaneously, thus instantaneously transitioning the PLL circuit between the active mode and slow mode.

Claims

1. A phase locked loop clock generator comprising:

a phase locking circuit for generating a first clock signal in response to a reference clock signal and a feedback clock signal; and

a frequency changer for generating a global clock signal for said phase locked loop clock generator and said feedback clock signal in response to said first clock signal, said frequency changer changing the frequency of said global clock signal in response to a control signal, with said reference clock signal and feedback clock signal being maintained at a first and second constant frequency, respectively.

2. The clock generator of claim 1 wherein said frequency changer includes a first divider for dividing said first clock signal to produce said global clock signal, and a second divider coupled to said first divider for dividing said global clock signal to produce said feedback clock signal.

3. The clock generator of claim 2 further comprising a frequency controller coupled to said first and second dividers for simultaneously changing the respective divisors of said first and second dividers.

4. The clock generator of claim 1 wherein said frequency changer also provides a peripheral clock signal.

18. The phase locked loop clock generator of claim 1 wherein said first and second constant frequencies are the same.

5. A phase locked loop feedback circuit useful in association with a system clock generator, said feedback circuit comprising a frequency changer for generating a global clock signal for said system clock generator and a feedback clock signal in response to a first clock signal said frequency changer changing the frequency of said global clock signal in response to a control signal, a reference clock signal and said feedback clock signal being maintained at a first and second constant frequency, respectively.

6. The feedback circuit of claim 5 wherein said frequency changer includes a first divider for dividing said first clock signal to produce said global clock signal, and a second divider coupled to said first divider for dividing said global clock signal to produce said feedback clock signal.

7. The feedback circuit of claim 6 further comprising a frequency controller coupled to said first and second dividers for simultaneously changing the respective divisors of said first and second dividers.

8. A method for generating a global clock signal comprising the steps of:

generating a first clock signal in response to a reference clock signal and a feedback clock signal; and

generating said global clock signal and said feedback clock signal in response to said first clock signal, said frequency of said global clock signal changing in response to an external control signal, with said reference clock signal and said feedback clock signal being maintained at a first and second constant frequency, respectively.

9. The method of claim 8 wherein the step of generating said global clock signal includes the step of dividing a first clock signal to produce a global clock signal.

10. The method of claim 9 wherein the step of generating said feedback signal includes the step of dividing said global clock signal to produce said feedback clock signal.

11. The method of claim 10 further comprising the step of changing the respective divisors of a first and second divider to change the frequency of said global clock signal.

12. The method of claim 8 wherein the step of generating said feedback signal includes the step of providing a peripheral clock signal.

19. The method of claim 8 wherein said first and second constant frequencies are the same.

13. A method for changing the frequency of a global clock signal generated by a phase locked loop generator having a first and second divider coupled in series, said method comprising the steps of:

changing the divisor of said first divider to change said frequency of said global clock signal produced at an output node of said first divider; and

simultaneously changing the divisor of said second divider to maintain a feedback clock signal produced at an output node of said second divider at a first constant frequency, with a reference clock signal provided to said generator being maintained at a second constant frequency.

14. The method of claim 13 wherein the step of generating said global clock signal includes the step of dividing a first clock signal to produce a global clock signal.

15. The method of claim 14 wherein the step of generating said feed back signal includes the step of dividing said global clock signal to produce said feedback clock signal.

16. The method of claim 15 further comprising the step of changing the respective divisors of said first and second dividers to change the frequency of said global clock signal.

17. A method of using a phase locked loop circuit to produce a global clock signal having an instantaneously changing frequency, said method comprising the steps of:

comparing an input clock signal with a PLL feedback signal;

generating a first clock signal in response to said comparing step;

dividing said first clock signal to produce said global clock signal;

dividing said global clock signal to produce said PLL feedback signal;

changing the divisor of said first dividing step to instantaneously change the frequency of said global clock signal; and

simultaneously changing the divisor of said second dividing step to maintain said PLL feedback signal at a first constant frequency, with said input clock signal provided to said generator being maintained at a second constant frequency.