Multi-loop .SIGMA. .DELTA. analog to digital converter

• US 5,982,315 A
• Filed: 09/12/1997
• Issued: 11/09/1999
• Est. Priority Date: 09/12/1997
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Bazarjani, Seyfollah S., Younis, Saed G.
• Primary Examiner(s): Williams, Howard L.
• Application Number:
  US08/928,874
• Time in Patent Office: 788 Days
• Field of Search: 341/143
• US Class Current: 341/143
• CPC Class Codes: H03M 3/372 Jitter reduction
• CPC Class Codes: H03M 3/406 by the use of a pair of integrators forming a closed loop
• CPC Class Codes: H03M 3/418 all these quantisers being single bit quantisers
• CPC Class Codes: H03M 3/47 using time-division multiplexing

Abstract

A bandpass ΣΔ DC utilizing either a single-loop or a MASH architecture wherein the resonators are implemented as either a delay cell resonator, a delay cell based resonator, a Forward-Euler resonator, or a two-path interleaved resonator. The resonator can be synthesized with analog circuit techniques such as active-RC, gm-C, MOSFET-C, switched capacitor, or switched current. The switched capacitor or switched current circuits can be designed using single-sampling, double-sampling, or multi-sampling circuits. The non-stringent requirement of a ΣΔ ADC using switched capacitor circuits allows the ADC to be implemented in a CMOS process to minimize cost and reduce power consumption. Double-sampling circuits provide improved matching and improved tolerance to sampling clock jitter. In particular, a bandpass MASH 4-4 ΣΔ ADC provides a simulated signal-to-noise ratio of 85 dB at an oversampling ratio of 32 for a CDMA application. The bandpass ΣΔ ADC can also be used in conjunction with undersampling to provide a frequency downconversion.

Claims

1. A sigma-delta analog-to-digital converter comprising:

a plurality of loops coupled in cascade, wherein each loop is implemented with multi-sampling circuitry, said multi-sampling circuitry configured to implement filter functions and to sample a respective loop input signal at multiple phases of a clock signal;

at least one feed-forward gain element, one gain element coupled between each pair of sequential loops; and

a noise cancellation logic coupled to each of said plurality of loop, said noise cancellation logic providing a converter output.

2. The converter of claim 1 wherein each loop comprises:

at least one filter section, said at least one filter section coupled in cascade; and

a quantizer coupled to a last filter section and to each of said at least one filter section.

3. The converter of claim 2 wherein each filter section comprises a resonator section.

4. The converter of claim 3 wherein each resonator section comprises:

a summer coupled to said quantizer;

a resonator coupled to said summer.

5. The converter of claim 1 wherein each loop includes at least one resonator, each resonator implemented as a delay cell based resonator, a lossless discrete integrator resonator, a Forward-Euler resonator, or a two-path interleaved resonator.

6. The converter of claim 1 wherein said multi-sampling circuitry is synthesized with an analog circuit technique selected from the group consisting of active-RC, gm-C, MOSFET-C, switched capacitor, and switched current.

7. The converter of claim 5 wherein said at least one resonator is implemented using double-sampling switched capacitor circuits.

8. The converter of claim 1 wherein each loop includes at least one delay cell resonator, each delay cell resonator comprises:

a gain element;

a summer coupled to said gain element;

a first delay element coupled to said summer; and

a second delay element coupled to said first delay element and said summer.

9. The converter of claim 8 wherein each delay element is implemented with a switched capacitor delay circuit.

10. The converter of claim 1 wherein said multi-sampling circuitry comprises double-sampling switched capacitor circuits that samples a respective loop input signal at alternative phases of a clock signal.

11. The converter of claim 1 wherein said multi-sampling circuitry comprises quadruple-sampling switched capacitor circuits.

12. The converter of claim 1 wherein each loop comprises:

at least one resonator section; and

a quantizer coupled to a last resonator section and to each of said at least one resonator section.

13. The converter of claim 12 wherein said resonator is selected from the group consisting of delay cell based resonator, lossless discrete integrator resonator, Forward-Euler resonator, and two-path interleaved resonator.

14. The converter of claim 13 wherein said resonator is synthesized with an analog circuit technique selected from the group consisting of active-RC, gm-C, MOSFET-C, switched capacitor, and switched current.

15. The converter of claim 12 wherein each resonator section is implemented using double-sampling switched capacitor circuits.

16. The converter of claim 12 wherein each resonator section is implemented using multi-sampling switched capacitor circuits.

17. A sigma-delta analog-to-digital converter comprising:

a plurality of loops coupled in cascade, each loop including at least one delay circuit, wherein each delay circuit comprises an amplifier and two or more signal paths, each signal path comprising;

a first switch;

a capacitor coupled to said first switch;

a second switch coupled to said capacitor and an AC ground;

a third switch coupled to said first switch and an output of said amplifier; and

a fourth switch coupled to said second switch and an input of said amplifier;

wherein each signal path in a particular delay circuit is clocked by a set of clock signals having clock phases unique from those of other signal paths in the particular delay circuit.

18. A sigma-delta analog-to-digital converter comprising:

a plurality of loops coupled in cascade, each loop including at least one delay cell and summer circuit, wherein each delay cell and summer circuit comprises an amplifier and two or more signal paths, each signal path comprising;

a first switch;

a first capacitor coupled to said first switch;

a second switch coupled to said first capacitor and said AC ground;

a third switch coupled to said first switch and said output of said loop in which said delay cell and summer circuit reside;

a second capacitor coupled to said first capacitor;

a fourth switch coupled to said second switch and an inverting input of said amplifier;

a fifth switch coupled to said second capacitor and said n-inverting output of said amplifier; and

a sixth switch coupled to said second capacitor and an inverting output of said amplifier within said delay circuit of said resonator section.

19. The converter of claim 18 wherein amplifiers within said delay cell and summer circuits are selected from the group consisting of telescopic amplifier, folded-cascade amplifier, and two-stage pole splitting amplifier.

20. The converter of claim 18 wherein a gain of said delay cell and summer circuit is implemented as the ratio of capacitor values of said first capacitor and said second capacitor within said delay cell and summer circuit.

21. The converter of claim 18 further comprising:

at least one feed-forward gain circuit, one feed-forward gain circuit coupled between each pair of sequential loops, each feed-forward gain circuit comprising at least two signal paths, each signal path comprising;

a first switch;

a capacitor coupled to said first switch;

a second switch coupled to said first capacitor and said AC ground; and

a third switch coupled to said second switch and said AC ground.

22. The converter of claim 21 wherein a gain of said feed-forward gain element is implemented as the ratio of capacitor values of said capacitor within said feed-forward gain circuit and said second capacitor within said delay cell and summer circuit to which said feed-forward gain circuit couples.

23. The converter of claim 18 wherein capacitor values of said capacitors within said delay cell and summer circuits are selected based on a noise calculation.

24. A sigma-delta analog-to-digital converter comprising:

a plurality of loops coupled in cascade, wherein each loop includes a quantizer implemented with two comparators, wherein one comparator is clocked by a switching clock having a first phase and another comparator is clocked by a switching clock having a second phase, and wherein said comparators provide differential outputs;

at least one feed-forward gain element, one gain element coupled between each pair of sequential loops; and

a noise cancellation logic coupled to each of said plurality of loop, said noise cancellation logic providing a converter output.

28. The converter of claim 24 further comprising:

a noise cancellation logic coupled to each of said two or more loops, said noise cancellation logic providing a converter output.

29. The converter of claim 24 wherein each loop is implemented with multi-sampling circuitry that samples a respective loop input signal at multiple phases of a clock signal.

30. The converter of claim 24 wherein each loop is implemented with double-sampling circuitry that samples a respective loop input signal at alternative phases of a clock signal.

31. The converter of claim 24 wherein each loop is implemented with switched capacitor circuits or switched current circuits.

33. The converter of claim 24 wherein said two or more loops are configured to provide bandpass sampling of a converter input signal.

25. A bandpass sigma-delta analog-to-digital converter comprising:

two or more loops coupled in cascade, each loop including a plurality of discrete delay elements;

a feed-forward gain element, one gain element coupled between each pair of adjacent loops; and

a noise cancellation logic coupled to each loop, said noise cancellation logic providing a converter output.

26. A sigma-delta analog-to-digital converter comprising:

two or more loops coupled in cascade; and

at least one feed-forward gain element, one feed-forward gain element coupled between each pair of sequential loops,

wherein a bias current of at least one of said two or more loops can be adjusted based on a required dynamic range.

32. The converter of claim 26 wherein said two or more loops are configured as a MASH architecture.

27. A sigma-delta analog-to-digital converter comprising:

two or more loops coupled in cascade; and

at least one feed-forward gain element, one feed-forward gain element coupled between each pair of sequential loops,

wherein at least one of said two or more loops can be disabled based on a required dynamic range.

34. A bandpass sigma-delta analog-to-digital converter comprising:

two or more loops coupled in cascade, wherein each loop is implemented with two or more interleaved high-pass signal paths; and

a feed-forward gain element, one feed-forward gain element coupled between each pair of sequential loops.

35. The bandpass converter of claim 34 further comprising:

a noise cancellation logic coupled to each loop, said noise cancellation logic combining outputs from said interleaved high-pass signal paths to provide a converter output.

36. The bandpass converter of claim 34 wherein said interleaved high-pass signal paths of each loop are clocked at different phases of a clock signal.

37. The bandpass converter of claim 34 wherein each interleaved high-pass signal path is implemented using at least one delay element.

38. A sigma-delta analog-to-digital converter comprising:

a plurality of loops coupled in cascade, each loop including at least one filter section, wherein each filter section is implemented with multi-sampling circuitry that samples a respective filter input signal at multiple phases of a clock signal; and

at least one feed-forward gain element, one gain element coupled between each pair of sequential loops.

39. The converter of claim 38 wherein said multi-sampling circuitry for each loop includes multiple signal paths, wherein each signal path is clocked by a set of clock signals having clock phases unique from those of other signal paths.

40. The converter of claim 38 wherein said multi-sampling circuitry for each loop includes two signal paths clocked at alternative phases of the clock signal.