System and method for triangle rasterization with frame buffers interleaved in two dimensions

• US 5,982,384 A
• Filed: 09/17/1996
• Issued: 11/09/1999
• Est. Priority Date: 06/08/1995
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Larson, Ronald D., Prouty, Bryan G., Dowdell, Charles R.
• Primary Examiner(s): Nguyen, Phu K.
• Application Number:
  US08/715,167
• Time in Patent Office: 1,148 Days
• Field of Search: 395/141, 395/143, 345/433, 345/418, 345/421, 345/440, 345/441, 345/443, 345/114, 345/118
• US Class Current: 345/441
• CPC Class Codes: G06T 11/40 Filling a planar surface by adding surface attributes, e.g. colour or texture
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A method and apparatus is provided for interleaving frame buffer controllers in two dimensions. Each frame buffer controller includes an edge stepper, a subspan stepper and a span stepper. The subspan stepper separates each span line into a plurality of parts. Each frame buffer controller provides pixel data for certain parts of the span line. The parts are defined by a start value, a stop value and a starting color value.

Claims

1. A frame buffer controller comprising:

an edge stepper receiving primitive data and generating a series of span line data representing opposing edges of the primitive data for each span line of a plurality of span lines of the pixel grid;

a subspan stepper receiving the series of span line data and generating, based upon the span line data for each span line of the series of span line data, a series of subspan data representing opposing edges of subspans within the opposing edges of the primitive data, each span line being separated into a plurality of subspans; and

a span stepper receiving each series of subspan data and generating pixel data corresponding to the subspan data.

2. The frame buffer controller of claim 1, wherein, for portions of a span line, said subspan data comprises:

a start value;

a stop value; and

a color start value.

3. The frame buffer controller of claim 2, wherein the portions of a span line defined by the subspan data vary based upon the span line.

4. The frame buffer controller of claim 3, wherein the portions of the span line are predetermined for each span line.

5. The frame buffer controller of claim 1, further comprising:

at least one memory for storing pixel data; and

at least one memory controller receiving the pixel data from the span stepper and storing pixel data in the at least one memory.

6. The frame buffer controller of claim 5,

wherein the pixel grid is separated into blocks of pixels each including at least one subblock of one or more pixels,

wherein the at least one memory controller comprises a plurality of memory controllers,

wherein pixel data for each subblock of pixel data generated by the span stepper is distributed to a predetermined memory controller.

7. The frame buffer controller of claim 1, wherein the span line data comprises:

a span line start value;

a span line stop value;

a span line color value; and

a span line color gradient value.

8. The frame buffer controller of claim 1, wherein each span line comprises two rows of pixels of a pixel grid.

9. The frame buffer controller of claim 1, wherein one or more of the plurality of subspans of each span line is assigned to the frame buffer controller.

10. A frame buffer system for a computer graphics system, the frame buffer system comprising:

a plurality of frame buffer controllers receiving primitive data from the computer graphics system, wherein each frame buffer controller includes;

an edge stepper for stepping along span lines of an edge of the primitive and for,generating span line data representing first portions of each span lines which are within the primitive;

a subspan stepper receiving the span line data corresponding to each span line and generating, for each span line, a series of subspan data representing second portions of a span line, the second portions being part of the first portion for each span line; and

a span stepper receiving the series of subspan data and generating pixel data for the primitive in the portions of the span lines represented by the subspan data.

11. The frame buffer system of claim 10, wherein the edge stepper of each frame buffer controller generates span line data corresponding to each span line.

12. The frame buffer system of claim 10, wherein the edge stepper of each frame buffer controller generates span line data corresponding to predetermined span lines.

13. The frame buffer system of claim 12, wherein the predetermined span lines are alternate span lines.

14. The frame buffer system of claim 10, further comprising at least one memory for storing the pixel data.

15. The frame buffer system of claim 14, wherein each frame buffer controller includes at least one memory controller for writing pixel data in the at least one memory.

16. The frame buffer system of claim 15, wherein the at least one memory comprises:

a plurality of memories corresponding to each of the plurality of frame buffer controllers,

wherein the at least one memory controller includes a plurality of memory controllers for each frame buffer controller, and

wherein alternating portions of the pixel data are provided to each of the plurality of memory controllers for each frame buffer controller for storage in a corresponding memory.

17. The frame buffer system of claim 14, wherein the at least one memory includes a plurality of memories corresponding to the plurality of frame buffer controllers.

18. The frame buffer controller of claim 10, wherein, for portions of a span line, said subspan data comprises:

a start value;

a stop value; and

a color start value.

19. The frame buffer system of claim 18, wherein the portions of a span line defined by the subspan data vary based upon the span line.

20. The frame buffer system of claim 18, wherein the portions of the span line are predetermined for each span line.

21. The frame buffer system of claim 10, wherein an entire span line is divided into portions of the span line covered by one of the plurality of frame buffer controllers.

22. The frame buffer controller of claim 10, wherein each span line comprises two rows of pixels of a pixel grid.

23. The frame buffer controller of claim 10, wherein each subspans comprises at least a portion of one or more blocks of pixels assigned to the frame buffer controller, wherein said start value and said stop value indicate pixel values in the blocks of pixels assigned to the frame buffer controller.

24. A method of operating a frame buffer controller comprising the steps of:

converting primitive data into first portions of span lines represented as span start and span stop values for each span line within the primitive;

dividing the first portion of each span line between the span start and span stop values into second portions corresponding to subspan sections of each span line; and

generating pixel data corresponding to selected ones of the subspan sections for the span lines.

25. The method of claim 24, further comprising the step of determining the plurality of subspan sections based upon the span line.