Method and apparatus for checking the resistance of programmable elements

• US 5,982,656 A
• Filed: 03/07/1997
• Issued: 11/09/1999
• Est. Priority Date: 03/07/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ho, Fan, Beigel, Kurt D., Debenham, Brett M., Pierce, Kim, Cutter, Douglas J., Mullarkey, Patrick J., Luong, Dien
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US08/813,767
• Time in Patent Office: 977 Days
• Field of Search: 365/96, 365/225.7, 365/203, 365/201, 327/525, 326/38, 324/550
• US Class Current: 365/96
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters

Abstract

Method and apparatus are disclosed for checking the resistance of programmable circuits in an integrated circuit where each programmable circuit includes a programmable element, such as an antifuse. A precharged node is connected to the programmable element and the voltage at the node discharges based on the resistance of the programmable element. An output signal is produced whose binary value is based on the voltage at the node after a sufficient time has elapsed to allow the initial voltage to discharge based on the resistance of the programmable element.

Claims

1. A method of checking the resistance of a programmable circuit in an integrated circuit, comprising the steps of:

precharging a node to an initial voltage;

connecting said programmable circuit to said node; and

generating an output signal whose binary value is based on the voltage that exists at said node after said programmable circuit is connected to the node.

2. Apparatus for checking the resistance of a programmable circuit in an integrated circuit, comprising:

circuitry defining a programmable circuit, said circuitry including a programmable element having a resistance;

circuitry for precharging a node to an initial voltage;

circuitry for connecting the programmable element in series with said precharged node; and

circuitry which generates an output signal whose binary value is based on the voltage in said node after said programmable element is connected to said node.

3. The apparatus of claim 2, wherein said programmable element comprises an antifuse element.

4. The apparatus of claim 2, wherein said programmable element comprises an ovonic element.

5. The apparatus for checking the resistance of a programmable element in an integrated circuit, comprising:

means for precharging a node to an initial voltage;

means for connecting said programmable element to said node; and

means for generating an output signal whose binary value is based on the voltage that exists at said node after the programmable element is connected to said node.

6. The apparatus of claim 5, wherein said programmable element comprises an antifuse element.

7. The apparatus of claim 5, wherein said programmable element comprises an ovonic element.

8. An integrated circuit, comprising:

a plurality of programmable circuits, each programmable circuit having a programmable element with a resistance;

a decoder for decoding a first address signal and sending a first enabling signal to each of said plurality of programmable circuits to selectively connect each programmable circuit to a node;

a precharged circuit for precharging said node to an initial voltage; and

an output signal generator for generating an output signal whose binary value is based on the voltage in said node after a given programmable circuit is connected to said node.

9. The apparatus of claim 8, wherein said programmable element comprises an antifuse element.

10. The apparatus of claim 8, wherein said programmable element comprises an ovonic element.

14. The integrated circuit of claim 8, wherein the precharged circuit comprises:

a test mode circuit for placing the integrated circuit in a test mode.

15. The integrated circuit of claim 14, wherein the test mode circuit generates a resistance check enabling signal in response to receiving a test mode signal.

16. The integrated circuit of claim 15, wherein the precharged circuit comprises a logic gate coupled to receive the resistance check enabling signal and a plurality of element selection signals, the logic gate delivering a signal to precharge the node in response to receiving at least the resistance check enabling signal.

17. The integrated circuit of claim 16, wherein each of the element selection signals are also delivered to each of the programmable circuits to selectively couple one of the programmable elements of each programmable circuit to the node for testing.

18. The integrated circuit of claim 17, wherein the test mode signal and the element selection signals are generated by automated test equipment.

19. The integrated circuit of claim 8, wherein the output signal generator comprises:

circuitry which detects a voltage across each selected programmable element and determines whether the detected voltage exceeds a threshold level to discriminate between a properly programmed programmable element and an improperly programmed programmable element.

11. A semiconductor memory device, comprising:

a memory array;

a plurality of programmable circuits, each programmable circuit having a programmable element with a resistance;

means for precharging a node to an initial voltage;

means for connecting each programmable circuit to said node; and

means for generating an output signal whose binary value is based on the voltage that exists at said node after a given programmable circuit is connected to said node.

12. The apparatus of claim 11, wherein said programmable element comprises an antifuse element.

13. The apparatus of claim 11, wherein said programmable element comprises an ovonic element.

20. A method of checking the resistance of a plurality of programmable circuits in an integrated circuit, comprising the steps of:

precharging a node to an initial voltage;

selectively connecting one of the plurality of programmable circuits to the node; and

generating an output signal whose binary value is based on the voltage that exists at the node after the programmable circuit is connected to the node.

21. The method of claim 20, wherein the step of precharging comprises the step of placing the integrated circuit into a test mode.

22. The method of claim 20, wherein the step of selectively connecting comprises the step of selectively coupling a programmable element of the selected programmable circuit to the node for testing.

23. Apparatus for checking the resistance of a programmable circuit in an integrated circuit, comprising:

a plurality of programmable circuits, each programmable circuit comprising a programmable element;

a precharging circuit coupled to a node, the precharging circuit charging the node to an initial voltage;

a selection circuit coupled to each of the plurality of programmable circuits, the selection circuit being operable to select one of the plurality of programmable circuits to couple the programmable element of each selected programmable circuit in series with the node; and

an output circuit which generates a binary output signal whose binary value is based on the voltage of the node after the programmable element is connected to the node.

24. The apparatus of claim 23, wherein the programmable element comprises an antifuse element.

25. The apparatus of claim 23, wherein the programmable element comprises an ovonic element.

26. An apparatus for checking the resistance of a plurality of programmable circuits in an integrated circuit, comprising:

means for precharging a node to an initial voltage;

means for selectively operably coupling one programmable circuit at a time to the node; and

means for generating a binary signal whose binary value is based on the voltage that exists at the node after the programmable circuit is operably coupled to the node.

27. The apparatus of claim 26, wherein each programmable circuit comprises a plurality of programmable elements, and wherein the coupling means comprises means for selectively coupling one of the plurality of programmable elements of the selected programmable circuit to the node.

28. An integrated circuit, comprising:

a plurality of programmable circuits, each programmable circuit having at least one programmable element;

a decoder for decoding a first address signal and sending a first enabling signal to each of the plurality of programmable circuits to selectively couple each programmable circuit to a node;

a precharging circuit for precharging the node to an initial voltage; and

an output signal generator for generating an output signal having a voltage correlative to a voltage on the node after a given programmable circuit is coupled to the node.

29. The apparatus of claim 28, wherein the programmable element comprises an antifuse element.

30. The apparatus of claim 28, wherein the programmable element comprises an ovonic element.

31. A method of determining the states of a plurality of programmable circuits on an integrated circuit, the integrated circuit also comprising a decoder, a precharging circuit, and an output signal generator, the method comprising the steps of:

coupling automated test equipment to the integrated circuit;

placing the integrated circuit into a test mode;

charging a node to an initial voltage using the precharging circuit in response to the integrated circuit being placed in the test mode;

generating a first address signal using the automated test equipment and delivering the first address signal to the decoder;

decoding the first address signal using the decoder, the decoder delivering an enable signal to a selected one of the plurality of programmable circuits to operably couple the selected programmable circuit to the node; and

delivering an output voltage signal using the output signal generator, the output voltage signal having a value correlative to a voltage at the node after the selected programmable circuit is operably coupled to the node.

32. The method of claim 31, wherein the step of placing comprises the step of:

generating a test mode initiation signal using the automated test equipment to place the integrated circuit into the test mode.

33. The method of claim 31, wherein the step of generating comprises the step of:

generating a second address signal using the automated test equipment and delivering the second address signal to a plurality of programmable elements in the selected programmable circuit, the second address signal selectively coupling one of the plurality of programmable elements to the node.

34. The method of claim 31, wherein the step of delivering the output signal comprises the step of:

delivering a binary signal having a binary value indicative of the state of the selected programmable circuit.