Method and apparatus for checking the resistance of programmable elements
First Claim
Patent Images
1. A method of checking the resistance of a programmable circuit in an integrated circuit, comprising the steps of:
- precharging a node to an initial voltage;
connecting said programmable circuit to said node; and
generating an output signal whose binary value is based on the voltage that exists at said node after said programmable circuit is connected to the node.
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Abstract
Method and apparatus are disclosed for checking the resistance of programmable circuits in an integrated circuit where each programmable circuit includes a programmable element, such as an antifuse. A precharged node is connected to the programmable element and the voltage at the node discharges based on the resistance of the programmable element. An output signal is produced whose binary value is based on the voltage at the node after a sufficient time has elapsed to allow the initial voltage to discharge based on the resistance of the programmable element.
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Citations
34 Claims
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1. A method of checking the resistance of a programmable circuit in an integrated circuit, comprising the steps of:
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precharging a node to an initial voltage; connecting said programmable circuit to said node; and generating an output signal whose binary value is based on the voltage that exists at said node after said programmable circuit is connected to the node.
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2. Apparatus for checking the resistance of a programmable circuit in an integrated circuit, comprising:
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circuitry defining a programmable circuit, said circuitry including a programmable element having a resistance; circuitry for precharging a node to an initial voltage; circuitry for connecting the programmable element in series with said precharged node; and circuitry which generates an output signal whose binary value is based on the voltage in said node after said programmable element is connected to said node. - View Dependent Claims (3, 4)
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5. The apparatus for checking the resistance of a programmable element in an integrated circuit, comprising:
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means for precharging a node to an initial voltage; means for connecting said programmable element to said node; and means for generating an output signal whose binary value is based on the voltage that exists at said node after the programmable element is connected to said node. - View Dependent Claims (6, 7)
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8. An integrated circuit, comprising:
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a plurality of programmable circuits, each programmable circuit having a programmable element with a resistance; a decoder for decoding a first address signal and sending a first enabling signal to each of said plurality of programmable circuits to selectively connect each programmable circuit to a node; a precharged circuit for precharging said node to an initial voltage; and an output signal generator for generating an output signal whose binary value is based on the voltage in said node after a given programmable circuit is connected to said node. - View Dependent Claims (9, 10, 14, 15, 16, 17, 18, 19)
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11. A semiconductor memory device, comprising:
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a memory array; a plurality of programmable circuits, each programmable circuit having a programmable element with a resistance; means for precharging a node to an initial voltage; means for connecting each programmable circuit to said node; and means for generating an output signal whose binary value is based on the voltage that exists at said node after a given programmable circuit is connected to said node. - View Dependent Claims (12, 13)
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20. A method of checking the resistance of a plurality of programmable circuits in an integrated circuit, comprising the steps of:
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precharging a node to an initial voltage; selectively connecting one of the plurality of programmable circuits to the node; and generating an output signal whose binary value is based on the voltage that exists at the node after the programmable circuit is connected to the node. - View Dependent Claims (21, 22)
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23. Apparatus for checking the resistance of a programmable circuit in an integrated circuit, comprising:
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a plurality of programmable circuits, each programmable circuit comprising a programmable element; a precharging circuit coupled to a node, the precharging circuit charging the node to an initial voltage; a selection circuit coupled to each of the plurality of programmable circuits, the selection circuit being operable to select one of the plurality of programmable circuits to couple the programmable element of each selected programmable circuit in series with the node; and an output circuit which generates a binary output signal whose binary value is based on the voltage of the node after the programmable element is connected to the node. - View Dependent Claims (24, 25)
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26. An apparatus for checking the resistance of a plurality of programmable circuits in an integrated circuit, comprising:
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means for precharging a node to an initial voltage; means for selectively operably coupling one programmable circuit at a time to the node; and means for generating a binary signal whose binary value is based on the voltage that exists at the node after the programmable circuit is operably coupled to the node. - View Dependent Claims (27)
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28. An integrated circuit, comprising:
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a plurality of programmable circuits, each programmable circuit having at least one programmable element; a decoder for decoding a first address signal and sending a first enabling signal to each of the plurality of programmable circuits to selectively couple each programmable circuit to a node; a precharging circuit for precharging the node to an initial voltage; and an output signal generator for generating an output signal having a voltage correlative to a voltage on the node after a given programmable circuit is coupled to the node. - View Dependent Claims (29, 30)
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31. A method of determining the states of a plurality of programmable circuits on an integrated circuit, the integrated circuit also comprising a decoder, a precharging circuit, and an output signal generator, the method comprising the steps of:
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coupling automated test equipment to the integrated circuit; placing the integrated circuit into a test mode; charging a node to an initial voltage using the precharging circuit in response to the integrated circuit being placed in the test mode; generating a first address signal using the automated test equipment and delivering the first address signal to the decoder; decoding the first address signal using the decoder, the decoder delivering an enable signal to a selected one of the plurality of programmable circuits to operably couple the selected programmable circuit to the node; and delivering an output voltage signal using the output signal generator, the output voltage signal having a value correlative to a voltage at the node after the selected programmable circuit is operably coupled to the node. - View Dependent Claims (32, 33, 34)
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Specification