Memory cell capable of storing more than two logic states by using different via resistances
First Claim
1. A memory circuit comprising:
- an array of vias forming a memory structure wherein each of said vias is selectively sized to set an associated storage state, wherein differing vias forming said array have differing sizes, wherein said each of the vias is coupled between a word line and a read line, wherein said each of the vias is configured to sustain a voltage drop when the word read line is asserted;
a diode coupled between the word read line and the data read line in series with said each of the vias, wherein the diode is configured to allow said each of the vias to sustain the voltage drop only when the word read line is asserted; and
an analog-to-digital converter coupled to said array of vias and configured to detect a voltage across selected ones of said vias to thereby determine said associated storage state of each of said selected vias, wherein the analog-to-digital converter is further configured to detect a value indicative of the voltage drop.
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Accused Products
Abstract
A process which enables storage of more than two logic states in a memory cell. In one embodiment, a via is used to couple a diode between a word read line and a data read line. The via has a resistance which is set to one of a plurality of values at the time of manufacture. When the word read line is asserted, the voltage drop sustained across the via is indicative of the stored logic state. An analog-to-digital (A/D) converter is coupled to the data read line so as to sense the voltage drop and determine the state represented. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit.
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Citations
19 Claims
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1. A memory circuit comprising:
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an array of vias forming a memory structure wherein each of said vias is selectively sized to set an associated storage state, wherein differing vias forming said array have differing sizes, wherein said each of the vias is coupled between a word line and a read line, wherein said each of the vias is configured to sustain a voltage drop when the word read line is asserted; a diode coupled between the word read line and the data read line in series with said each of the vias, wherein the diode is configured to allow said each of the vias to sustain the voltage drop only when the word read line is asserted; and an analog-to-digital converter coupled to said array of vias and configured to detect a voltage across selected ones of said vias to thereby determine said associated storage state of each of said selected vias, wherein the analog-to-digital converter is further configured to detect a value indicative of the voltage drop. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A memory circuit comprising:
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an array of vias forming a memory structure, wherein each of said vias is selectively sized to set an associated storage state, wherein the associated storage states include at least three states, wherein differing vias forming said array have differing sizes each corresponding to one of the at least three states, wherein said each of the vias is coupled between a word line and a read line, wherein said each of the vias is configured to sustain a voltage drop when the word read line is asserted; and an analog-to-digital converter coupled to the array of vias and configured to detect a voltage across selected ones of said vias to thereby determine said associated storage state of each of said selected vias, wherein the analog-to-digital converter is further configured to detect a value indicative of the voltage drop; wherein said each of the vias has a size which is set to determine the voltage drop. - View Dependent Claims (14, 15, 16, 17)
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18. A memory circuit comprising:
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an array of vias forming a memory structure wherein each of said vias is selectively sized to set an associated storage state, wherein differing vias forming said array have differing sizes, wherein said each of the vias is coupled between a word line and a read line, wherein said each of the vias is configured to sustain a voltage drop when the word read line is asserted; and an analog-to-digital converter coupled to said array of vias and configured to detect a voltage across selected ones of said vias to thereby determine said associated storage state of each of said selected vias, wherein the analog-to-digital converter is further configured to detect a value indicative of the voltage drop; wherein said each of the vias has a resistance which is set to determine the voltage drop, and wherein said resistance is set to one of at least three magnitudes.
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19. A memory circuit comprising:
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an array of vias forming a memory structure, wherein each of said vias is selectively sized to set an associated storage state, wherein the associated storage states include at least three states, wherein differing vias forming said array have differing sizes each corresponding to one of the at least three states, wherein said each of the vias is coupled between a word line and a read line, wherein said each of the vias is configured to sustain a voltage drop when the word read line is asserted; a diode coupled between the word read line and the data read line in series with said each of the vias, wherein the diode is configured to allow said each of the vias to sustain the voltage drop only when the word read line is asserted; and an analog-to-digital converter coupled to the array of vias and configured to detect a voltage across selected ones of said vias to thereby determine said associated storage state of each of said selected vias, wherein the analog-to-digital converter is further configured to detect a value indicative of the voltage drop.
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Specification