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Memory cell capable of storing more than two logic states by using different via resistances

  • US 5,982,659 A
  • Filed: 12/23/1996
  • Issued: 11/09/1999
  • Est. Priority Date: 12/23/1996
  • Status: Expired due to Term
First Claim
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1. A memory circuit comprising:

  • an array of vias forming a memory structure wherein each of said vias is selectively sized to set an associated storage state, wherein differing vias forming said array have differing sizes, wherein said each of the vias is coupled between a word line and a read line, wherein said each of the vias is configured to sustain a voltage drop when the word read line is asserted;

    a diode coupled between the word read line and the data read line in series with said each of the vias, wherein the diode is configured to allow said each of the vias to sustain the voltage drop only when the word read line is asserted; and

    an analog-to-digital converter coupled to said array of vias and configured to detect a voltage across selected ones of said vias to thereby determine said associated storage state of each of said selected vias, wherein the analog-to-digital converter is further configured to detect a value indicative of the voltage drop.

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