Semiconductor memory capable of writing and reading data

• US 5,982,664 A
• Filed: 09/24/1998
• Issued: 11/09/1999
• Est. Priority Date: 10/22/1997
• Status: Expired due to Term

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Watanabe, Kenichi
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US09/159,660
• Time in Patent Office: 411 Days
• Field of Search: 365/185.11, 365/185.22, 365/185.29, 365/185.33, 365/218, 365/230.03
• US Class Current: 365/185.11
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2216/22 Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously

Abstract

A nonvolatile semiconductor memory serving as a semiconductor memory which is capable of erasing data in a batch comprises four banks constituting a storage circuit, a bank control circuit for instructing access to respective banks (writing, reading, etc.), and a status signal output circuit connected to the bank control circuit. The status signal output circuit outputs status signals for instructing access status of respective banks. The status signals are outputted to an external device through a data bus. With such a construction, the access status of respective banks can be easily grasped, so that the data access to the semiconductor memory can be enhanced with efficiency, thereby realizing high speed data processing.

Claims

1. A semiconductor memory capable of writing and reading data in units of banks, wherein a predetermined number of memory cells is defined as one bank, said semiconductor memory comprising:

a storage circuit composed of a plurality of banks for storing data therein;

a control circuit, coupled to the storage circuit, which outputs a control signal for controlling reading and writing of data within the banks of the storage circuit; and

a status signal output circuit, coupled to the control circuit, which generates and outputs a plurality of status signals respectively indicative of a read/write processing status of the plurality of banks of the storage circuit.

2. The semiconductor memory according to claim 1, wherein the data and the status signals are transmitted through a data bus.

3. The semiconductor memory according to claim 1, wherein the status signal output circuit simultaneously outputs the plurality of status signals in parallel.

4. The semiconductor memory according to claim 1, wherein the status signal output circuit sequentially outputs the plurality of status signals.

5. The semiconductor memory according to claim 1, further comprising a selection circuit for selecting one of the banks and causing the status signal output circuit to output a corresponding status signal for the selected bank.

6. The semiconductor memory according to claim 1, wherein the storage circuit verifies whether data is normally written or not within the respective banks, and wherein the status signals include a signal for indicating the result of the verification.

7. The semiconductor memory according to claim 6, wherein the semiconductor memory is a nonvolatile semiconductor memory capable of electrically rewriting data.

8. The semiconductor memory according to claim 3, wherein the status signals comprise at least a first signal for instructing write status and a second signal for instructing a read status, and wherein signals serving as predetermined status signals and corresponding to the first signal and the second signal relative to respective banks are sequentially outputted.

9. The semiconductor memory according to claim 8, wherein the storage circuit verifies whether data is normally written or not within the respective banks, and wherein the status signals include a signal for indicating the result of the verification.

14. The semiconductor memory according to claim 1, further comprising a selection circuit for selecting one of the banks and causing the status signal output circuit to output a status signal for the selected bank.

10. A nonvolatile semiconductor memory capable of writing and reading data in units of banks, wherein a predetermined number of memory cells is defined as one bank, said nonvolatile semiconductor memory comprising:

a storage circuit composed of a plurality of banks for storing data therein;

a control circuit, coupled to the storage circuit, which outputs a control signal for controlling reading and writing of data within the banks of the storage circuit; and

a status signal output circuit coupled to the control circuit, which generates and outputs a plurality of status signals leading out of the semiconductor memory and respectively indicating operational processing states of the plurality of the banks of the storage circuit.

11. The semiconductor memory according to claim 10, wherein the data and the status signals are transmitted through a data bus.

12. The semiconductor memory according to claim 10, wherein the status signal output circuit simultaneously outputs the plurality of status signals in parallel.

13. The semiconductor memory according to claim 10, wherein the status signal output circuit sequentially outputs the plurality of status signals.

15. A nonvolatile semiconductor memory capable of writing and reading data in units of banks, wherein a predetermined number of memory cells is defined as one bank, said nonvolatile semiconductor memory comprising:

a storage circuit composed of a plurality of banks for storing data therein, the storage circuit verifying whether data is normally written within the banks;

a control circuit, coupled to said storage circuit, which outputs a control signal for controlling reading and writing of data within the banks of the storage circuit; and

a status signal output circuit, coupled to the control circuit, which generates and outputs a plurality of status signals leading out of the semiconductor memory and respectively indicating a write/read status of the plurality of banks and a result of verification of data in the storage circuit.

16. The semiconductor memory according to claim 15, wherein the data and the status signals are transmitted through a data bus.

17. The semiconductor memory according to claim 15, wherein the status signal output circuit simultaneously outputs the plurality of status signals in parallel.

18. The semiconductor memory according to claim 15, wherein the status signal output circuit sequentially outputs the plurality of status signals.

19. The semiconductor memory according to claim 15, further comprising a selection circuit for selecting one of the banks and causing the status signal output circuit to output a status signal for the selected bank.